Barcelona Design, Inc.

Sabio Labs, Inc.

Arash Hassibi

Stephen P Boyd

David M Colleran

Maria Del Mar Hershenson

Mar Hershenson

Andre Hentz

Dave Colleran

Lungying Fong

A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.

Automatic phase lock loop design using geometric programming

A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved numerically with great efficiency. Prior work discloses the design of many different analog circuit cells such as operational amplifiers, spiral inductors, and LC oscillators which can be cast as geometric programs. The present disclosure adds to this layout floorplanning constraints in posynomial form that can be mixed with design constraints for different analog circuits. This allows the simultaneous design and floorplanning of numerous analog circuits using geometric programming. Thus, the design and floorplanning can be performed optimally in a single step.

Optimal simultaneous design and floorplanning of integrated circuit

A method is described that involves recognizing that a variable within a monomial or posynomial expression for a characteristic of an analog or mixed signal system has a dependency on a lower level expression. Then, retrieving from a database the lower level expression and substituting it into the expression in place of the variable so as to describe the system at a greater level of detail than the variable did.

Method and apparatus for automatic analog/mixed signal system design using geometric programming

In one embodiment, the invention is a method. The method is a method of routing a circuit having a set of nets and a set of circuit elements specified as a slicing tree and a set of linear constraints. The method includes finding short paths for the set of nets based on a minimum-spanning-tree solution to a floorplan derived from the slicing tree for each net of the set of nets. The method also includes routing the nets as conductors within channels of the floorplan, the conductors having locations satisfying a set of linear constraints based on the solution of a linear optimization problem.

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Mountain View, CA, United States of America

Arash Hassibi