Inphi Corporation

Marvell Asia Pte., Ltd.

Cortina Systems Corporation

Applied Micro Circuits Corporation

Arash Farhoodfar

Benjamin P Smith

Sudeep Bhoja

Jamal Riani

Andrew Hunt

Frank Robert Kschischang

Whay Sing Lee

Volodymyr Shvydun

Shaun Lytollis

Michael Duckering

Vipul Bhatt

Stewart N Crozier

Jitendra Kumar Swarnkar

Scott Feller

Andre Sczapanek

Sean Batty

Srinivas Swaminathan

Andre Szczepanek

Todd Rope

Juan-Carlos Calderon

Jean-Michel Caia

John Lodge

Arun Zarabi

Radhakrishnan L Nagarajan

Wei Fu

Michael Lewis Takefman

Viet Linh Do

Stephane Dallaire

Travis William Lovitt

Kumaran David Siva

Tarun Setya

Michael Raymond Miller

Ilya Lyubomirsky

Belal Helal

Devin Linnington

Vlad Shyvdun

In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.

In-band DSP management interface

The present invention relates to data communication systems and methods thereof. In a specific embodiment, a receiver includes a trigger circuitry that selects a subset of encoded data blocks to measure the performance of a communication lane. Partial syndromes—based on these partial data blocks—are used in partial syndrome calculations, and they are later combined to form full syndromes. A decoder is configured to decode the full syndromes. There are other embodiments as well.

Systems and methods for performance monitoring with forward error correction mechanism

A transmitter includes: an input configured to receive, via an electrical interface, encoded data from a host device, the encoded data being encoded at the host device according to a first code; processing circuitry configured to process the encoded data to provide processed data; an encoder configured to encode the processed data according to a second code that is different than the first code, where encoding the processed data includes concatenating one or more parity bits to the processed data to provide forward error correction (FEC) blocks of data; and transmit circuitry to transmit the FEC data over an optical medium.

Optical transmitter with encoder encoding processed data including concatenating parity bits to generate fec data blocks

An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.

Circuit for multi-path interference mitigation in an optical communication system

A system includes memory, a controller and a processor. The controller receives program instructions to program the controller to perform function, and handle data as a result of performing the function. The processor: performs an initial configuration of a map to proportion the memory including allocating first and second portions of the memory for the program instructions and the data, the map being indicative of addresses of the first and second portions; subsequent to performing the initial configuration, reconfigures the map to change amounts of the memory allocated for the program instructions and the data, and prior to and subsequent to reconfiguring the map and based on the map, routes the program instructions and data between the controller and the memory, stores the program instructions at the addresses of the memory allocated for the program instructions, and stores the data at the addresses of the memory allocated for the data.

Memory allocation and reallocation for program instructions and data using intermediate processor

A cable assembly includes connectors and protection switching circuitry. A first connector connects the cable assembly to a first switch, which has a first network path to a first host device. A second connector connects the cable assembly to a second switch, which has a second network path to the first host device. A third connector is connected to the first and second connectors via respectively a first cable and a second cable and connects the cable assembly to a second host device. The protection switching circuitry is embedded in the cable assembly and: establishes a communications connection to transfer data between the host devices using a first data path, which includes the first network path, connector, cable, and switch; determines the first data path is degraded; and in responsive, switches the communications connection to a second data path, which includes the second network path, connector, cable, and switch.

Cable assembly with protection switching

A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

Network transceiver with clock sharing between dies

An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.

Methods and systems for data transmission

A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

Soft FEC with parity check

Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.

Optimizing host / module interface

The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

Protection switching device with link selective switching between host devices for maintenance of communication connection

A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.

Networking switching devices and methods thereof

Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.

Memory allocation and reallocation for memory access instructions and data using intermediate processor

A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.

Growing community of inventors

Santa Clara, CA, United States of America

Arash Farhoodfar