Stmicroelectronics International N.v.

Apurva Sen

Rakesh Malik

Tejinder Kumar

Rathod Ronak Kishorbhai

Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

Growing community of inventors

Ghaziabad, India

Apurva Sen