Samsung Electronics Co., Ltd.

Arm Limited

Apurva Patel

Hien Le

Ashok Kumar Tummala

Vikas Sinha

Tarun Nakra

Rishabh Jain

Mark Gerald LaVine

Yingying Tian

Sai Kumar Marri

Omar Torres

Ranjini Mysore Nagaraju

Surabhi Garg

Fnu Parshant

A mechanism is provided efficient packing of network flits in a data processing network. Transaction messages for transmission across a communication link of a data processing network are analyzed to determine a group of transaction messages to be passed to a packing logic block for increased packing efficiency. The transaction messages are packed into slots of one or more network flits and transmitted across a communication link. The mechanism reduces the number of unused slots in a transmitted network.

Method and apparatus for efficient packing of flow control units

A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

Traffic isolation at a chip-to-chip gateway of a data processing system

According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Speculative DRAM read, in parallel with cache level search, leveraging interconnect directory

A method includes: receiving a coherent request from a requester; looking up a state array of a snoop filter table corresponding to an index identified by the coherent request; determining state information corresponding to the coherent request; and determining to access one or more address tag arrays of the snoop filter table based on one or more of the state information, the requester, and a type of the coherent request.

Power efficient snoop filter design for mobile platform

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Austin, TX, United States of America

Apurva Patel