Texas Instruments Corporation

April Gurba

Rajesh B Khamankar

Husam N Alshareef

Mark H Somervell

Brian Keith Kirkpatrick

Malcolm John Bevan

Clinton L Montgomery

Hiroaki Niimi

James Joseph Chambers

Douglas Ticknor Grider

Toan Tran

Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().

Reliable high voltage gate dielectric layers using a dual nitridation process

The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Dual-gate integrated circuit semiconductor device

The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (). The nitrided oxide dielectric layer is exposed to an etch process (). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.

Monitoring of nitrided oxide gate dielectrics by determination of a wet etch

Post high voltage gate dielectric pattern plasma surface treatment

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Plano, TX, United States of America

April Gurba