At&t Bell Laboratories

At&t Technologies, Inc.

American Telephone and Telegraph Company, At&t Technologies, Inc.

At&t Laboratories, Limited

Apparajan Ganesan

Ronald A Morrison

Richard G Beale

Kenneth R Laker

Paul E Fleischer

Scott H Early

Wayne Allen Weise

Klye L Burson

Scott O Campbell

Kyle L Burson

A voltage comparator (10) includes two sampled input networks connected in arallel between an input reference voltage (Vref) and the inverting input (16) of an integrator (12,14), the other input (18) of which is grounded. The first input network has a first input capacitor (C1) which is through-switched at a first sampling frequency (F1). The second input network has a second input capacitor which is diagonally-switched at a second sampling frequency (F2), thus providing an output voltage to the integrator (12,14) which is of opposite polarity to that of the first network. For a given ratio between the capacitors (C1,C2), the output (15) of the integrator is determined by the relationship between the sampling frequencies (F1,F2), thus providing a comparator capability. Also disclosed is a frequency lock loop (34) in which the output (Vcontrol) of a frequency comparator (38) is filtered of the switching frequencies and utilized as the control voltage for a voltage controlled oscillator (42). The output of the oscillator is then coupled to a switching pulse generator (44) which provides the switching pulses (F2,F2N) to the second input network of the comparator (38).

Frequency comparator circuits

A capacitive keypad (24) is scanned in such a manner that the capacitance value (C) of an individual key in a given row is multiplied by the sum of the relative capacitance values of all the other keys in the same row by means of an amplifier (32) to generate a combined pulse. The combined pulse is then compared by a comparator (28) to a threshold voltage (Vref 3) to verify whether the individual key in question is in the closed or open position. The verification can be made independently of keypad-to-keypad variations in the capacitances of the keys, since the combined pulse value does not depend upon the absolute capacitance value of the keys, but only upon their relative values. Also disclosed is a method for scanning to determine the presence of multiple key closures. This involves comparing the capacitance of an interrogated key to not only the sum of the other capacitors of its row, but also to the sum of the capacitors of the other rows and columns and a comparison of the resulting value to that generated by previous scans to detect change.

Method and apparatus for capacitive keyboard scanning

A Schmitt trigger circuit 10 includes a pair of transmission gates 20, 22 connected, respectively, between a pair of threshold voltages V.sub.tH, V.sub.tL and the threshold input port 16 of a comparator 12. The control lead of one transmission gate 20 is connected to the output 18 of the comparator 12 through an inverter 24. The control lead of the other transmission gate 22 is connected directly to the output 18 of the comparator 12. The other input port 14 of the comparator 12 receives the signal input. Also disclosed is a circuit 26 for generating the reference voltages V.sub.tH, V.sub.tL. The circuit 26 includes an operational amplifier 28 driving a complementary pair of current mirrors (M1, M3, M5; M4, M6) which force current through a pair of resistors (R.sub.H, R.sub.L) to ground potential. The resistors (R.sub.H, R.sub.L) provide stable reference potentials.

Schmitt trigger circuit

A CMOS circuit (10) for preventing overvoltage between two supply nodes (12,14) makes use of vertical NPN bipolar transistors (80,84) for their current-carrying capability. Zener diodes (16,18,20,22) and a resistor (24) generate a sensing voltage which is amplified by a vertical bipolar transistor (28) and coupled to one input of a comparator (40) which has the other input at a bias voltage node (52) of a voltage divider (54,56,58,60). The comparator output (50) is coupled to the input of a transimpedance transistor (72) which drives the input current of a current mirror (66,74). The output (78) of the current mirror turns on the current-carrying transistors (80,84). Positive feedback for latching is provided by connecting the common gates of the current mirror transistors to the gate of a feedback transistor (86) which has its current path connected between the one supply node and the base (26) of the first bipolar transistor. The vertical bipolar transistors (28,80,84) of the circuit include guard rings (37) of heavily doped material about the emitter (32) and base (34) regions at the surface and tied to the collector voltage.

CMOS Circuit overvoltage protection

Two input stages (10,12) are interconnected so that their input common mode voltage ranges to one side of signal ground are combined to provide a common mode voltage range substantially equal to the supply voltage. One stage has N-channel differential input transistors (N1,N2), while the other stage has P-channel differential input transistors (P3,P4). The input current branches of the stages are interconnected by current mirror transistors (N6,N7) so that signal current is shared. The output (22) is taken from one branch of the N-type stage (10) and coupled to an output stage (24) with frequency compensation (C,R).

CMOS Operational amplifier

The input (16) and output (20) MOS transistors of a current mirror (10) have their sources connected to a supply voltage node (12). The gate of the input transistor (16) is connected to its drain and is also connected to the gate of the output transistor (20) through an isolation switch (24). The gate of the output transistor (20) is connected to the supply voltage node (12) through a disable switch (26). Closing of the disable switch (26) and opening of the isolation switch (24) turns off current in the output transistor (20). Opening the disable switch (26) and closing the isolation switch (24) turns the output current on again. Also disclosed is a mirror (28) having switches (30), (32) configured for various logic functions. A voltage-controlled oscillator (34) and a phase detector circuit 72 having a switched current input provided by switched current mirrors (40, 42, 80, 82) is described.

Switched current mirror

A switched capacitor biquadratic filter (10; 20) includes means for dynamically shifting the level of the input voltage (V.sub.B, V.sub.D ; V.sub.X, V.sub.Y,) of the amplifiers (12, 14), so that the need for a level shifting stage in the amplifiers (12; 14) is eliminated. The normally grounded nodes associated with the input ports of the amplifiers (12; 14) are set to a reference voltage (V.sub.B, V.sub.D ; V.sub.X, V.sub.Y) which shifts the inputs to a level appropriate to result in an analog grounded voltage at the outputs of the amplifiers. Internal level shifting stages are thereby eliminated from the amplifiers (12; 14). This gives the filter (10, 20) a broader operating frequency range. Also disclosed is a particular design for the amplifiers (12, 14) which includes a folded cascode mirror configuration.

Switched capacitor circuits

A switched capacitor oscillator is constructed by providing a damped resonator network with a comparator as a nonlinear feedback element by connecting the input of the comparator to the output of a first operational amplifier of the resonator network and connecting the output of the comparator to the input of the resonator network. The comparator thus becomes a saturable positive feedback element for the resonator network. Also disclosed is a startup network for the oscillator and an input network which derives an input from a reference voltage in order to eliminate supply voltage noise and provide precision control of amplitude.

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Indianapolis, IN, United States of America

Apparajan Ganesan