Nvidia Corporation

Apoorv Parle

Jack H Choquette

Ronny Krashinsky

Shirish C Gadre

Lacky V Shah

John H Edmondson

Olivier Giroux

Manan Patel

Ravi Kiran Manyam

Wish Gandhi

Prakash Bangalore Prabhakar

Steve Heinrich

Jerome Francis Duluk, Jr

Luke Durant

Gentaro Hirota

Brian S Pharris

Ze Long

Jeff Tuckey

Harold Carter Edwards

Rajballav Dash

Greg Palmer

Gokul Ramaswamy Hirisave Chandra Shekhara

Aditya Avinash Atluri

Sandeep Navada

Eric Werness

Naman Govil

Shayani Deb

Sean Jeffrey Treichler

Alexander Lev Minkin

Andrew Robert Kerr

Rui Guo

Alan Kaatz

Rishkul Kulkarni

Girish Bharambe

Kyrylo Perelygin

Maciej Piotr Tyrlik

Konstantinos Kyriakopoulos

Edward H Gornish

Cris Cecka

James Player

Aman Arora

Cody Addison

Vijay Thakkar

Haicheng Wu

David Allan Berson

Bageshri Sathe

David Dastous St Hilaire

Subhasmita Chakraborty

Vikram Dhar

Vishalkumar Ketankumar Mehta

Balaji Krishna Yugandhar Atukuri

Chao Li

Apparatuses, systems, and techniques to cause information to be provided. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause an amount of information to be accessed as a result of one or more memory transactions to be provided to one or more users.

Application programming interface to provide information

A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Cooperative group arrays

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

Distributed shared memory

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Application programming interface to wait on matrix multiply-accumulate

This specification describes a programmatic multicast technique enabling one thread (for example, in a cooperative group array (CGA) on a GPU) to request data on behalf of one or more other threads (for example, executing on respective processor cores of the GPU). The multicast is supported by tracking circuitry that interfaces between multicast requests received from processor cores and the available memory. The multicast is designed to reduce cache (for example, layer 2 cache) bandwidth utilization enabling strong scaling and smaller tile sizes.

Programmatically controlled data multicasting across multiple compute engines

Growing community of inventors

San Jose, CA, United States of America

Apoorv Parle