Sun Microsystems, Inc.

Oracle International Corporation

Oracle America, Inc.

Aparna Ramachandran

Gajendra Prasad Singh

Shree Kant

Robert Paul Masleid

Claude R Gauthier

Brian W Amick

Tri K Tran

Dong Joon Yoon

Gary John Formica

James Ballard

Kiran Kishore Vedantam

Miao Rao

Duncan C Collier

Sampanna Prashant Pathak

Mark Russell O'brien

King Yen

Ranjan Vaish

A method may include obtaining a design including cells and a power grid. The method may further include dividing the design into tiles, determining a voltage budget for a tile, calculating a voltage drop for each cell of the tile based on determining an activity factor for the cell and a peak current consumed by the cell, determining, for each cell of the tile and based on the power grid, an affected vicinity for the cell including one or more neighboring cells affected by a current drawn on the cell, determining an affected vicinity for the tile based on the affected vicinity for each cell of the subset, calculating a voltage drop for the tile based on the voltage drop for each cell of the affected vicinity for the tile, and detecting a voltage deviation when a difference between the voltage budget and the voltage drop exceeds a threshold.

Adaptive power grid generation

A multi-layer full dense mesh (MFDM) device. The MFDM may include a metal-top layer including a bump pad array that may include a power(PWR) bump pad within a PWRbump region, a VSS bump pad within a VSS bump region, and a power(PWR) bump pad within a PWRbump region. The metal-top layer may also include a PWRmajority metal-top region. The MFDM may also include a metal-top-layer beneath the metal-top layer and including a VSS majority metal-top-region, a PWRmetal-top-region, and a PWRmetal-top-region. The MFDM may also include a metal-top-layer beneath the metal-top-layer and including a PWRmajority metal-top-region, a VSS metal-top-region, and a PWRmetal-top-region. The MFDM may also include top-VIAs disposed between the metal-top layer and the metal-top-layer, and top-VIAs disposed between the metal-top-layer and the metal-top-layer.

Multi-layer full dense mesh

A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.

Die power structure

A zipper structure includes a first contiguous full-dense-mesh (FDM) array of a first circuit in top metal and a second contiguous FDM array of a second circuit in top-1 metal, a third contiguous FDM array of the second circuit in top metal and a fourth contiguous FDM array of the first circuit in top-1 metal, and a signal line, such that portions of the first contiguous FDM array and the second contiguous FDM array overlap and portions of the third contiguous FDM array and the fourth contiguous FDM array overlap. The Zipper structure facilitates connecting the first contiguous FDM array to the fourth contiguous FDM array by vias and a first connector lines and the second contiguous FDM array to the third contiguous FDM array by vias and a second connector lines, such that portion of the signal line overlaps with the first connector lines and the second connector lines.

Combined power mesh transition and signal overpass/underpass

A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.

Generating different delay ratios for a strobe delay

A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.

Digital delay locked loop with extended phase capture range

A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A connecting load device of each memory cell is connected to either a first or a second of the pair of bitline segments. An equal number of load devices in each column couple to each of the pair of bitlines.

Methods and circuits for balancing bitline precharge

A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.

Low power memory design with asymmetric bit line driver

An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.

Growing community of inventors

Cupertino, CA, United States of America

Aparna Ramachandran