Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

Commissariat a L'energie Atomique

Other

Koninklijke Philips Corporation N.v.

Stmicroelectronics S.r.l.

France Telecom

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Stmicroelectronics (rousset) Sas

Aomar Halimaoui

Daniel Bensahel

Christelle Charpin-Nicolle

Benoit Froment

Philippe Coronel

Shay Reboh

Yves Morand

Claire Fenouillet-Beranger

Emmanuel Augendre

Sylvain Maitrejean

Yves Campidelli

Sylvain Barraud

Guillaume Rodriguez

Sophie Bernasconi

Rebha El Farhane

Marc Zussy

Jean-Charles Barbe

Jean-Michel Hartmann

Stéphane Monfray

Damien Lenoble

Pascale Mazoyer

Christophe Dubarry

Florian Pebay-Peyroula

Andre Schiltz

Daniel-Camille Bensahel

Olivier Kermarrec

Claire Gallon

Laurent Ortiz

Claire Fenouillett-Beranger

Sylvian Barraud

Guillermo Bomchil

Ernesto Perea

Jean Marc Francou

Magali Tessaire

Cécile Moulin

A microelectronic device is provided, including: a support; and an electrically conductive element including in a stack and successively above a first face of the support, a first layer based on a metal and a second layer, in contact with the first layer, based on a material selected from among MoSi and WSi. A method for manufacturing the microelectronic device is also provided.

Electrically conductive element

A method for securing an integrated circuit upon making it includes the steps of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.

Method for securing an integrated circuit upon making it

The present invention relates to a memory device comprising a first electrode (), a second electrode () and an active portion that can change conductive state, positioned between a first face of the first electrode () and a first face of the second electrode (). The first electrode () comprises an upper portion forming the first face of the first electrode (). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer ().

Method of manufacturing a memory device

The electrode for a structure of Metal-Insulator-Metal type is formed by a stack successively comprising a gold layer, a barrier layer made from electrically conducting oxide and a platinum layer. The electrically conducting oxide is advantageously a noble metal oxide, and preferentially ruthenium oxide. The electrode is arranged on a substrate. The gold layer of the electrode is separated from the substrate by an adhesion layer made from titanium dioxide. The electrode is used to fabricate a capacitor of Metal-Insulator-Metal type.

Electrode for a metal-insulator-metal structure, capacitor of metal-insulator-metal type, and method for fabricating one such electrode and one such capacitor

A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG.A).

Method for causing tensile strain in a semiconductor film

An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

Method for forming integrated circuits on a strained semiconductor substrate

The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

Method of forming a strained silicon layer

A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.

Method for making a semi-conducting substrate located on an insulation layer

A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.

Process for assembling two wafers and corresponding device

A housing includes a body with a first silicon element and a second porous silicon element, at least one first cavity provided in the porous silicon element, a first electrically conducting contact area electrically coupled to at least a portion of at least one internal wall of the at least one first cavity, and a second electrically conducting contact area electrically coupled to a different portion of the at least one internal wall of the second porous silicon element of the at least one first cavity, wherein the two contact areas are electrically isolated from each other.

Housing, in particular for a biofuel cell

An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (or) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.

Integrated circuit comprising a capacitor with HSG metal electrodes

A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.

Method for manufacturing a structure of semiconductor-on-insulator type

Integrated circuit comprising a capacitor with metal electrodes and process for fabricating such a capacitor

Growing community of inventors

La Terrasse, France

Aomar Halimaoui