Cadence Design Systems, Inc.

Invarium, Inc.

Anwei Liu

Abdurrahman Sezginer

Chi-Song Horng

Bayram Yenikaya

Devendra Joshi

Michiel Victor Paul Kruger

Wolf Staud

According to various embodiments of the invention systems and methods for multiple pattern lithography, wherein a target layout pattern that is not capable of being printed in one lithography step is decomposed into multiple patterns that are printable in one lithography operation and, when appropriate, a continuous junction is utilized for where patterns overlap. In a further embodiment, where a continuous junction is not utilized, a splice is utilized at overlap locations. In yet another embodiment, where splices are utilized for overlap locations, identifying where critical nets are located in the target layout pattern, determining how close a component of the critical net is to a splice, and changing the target layout pattern as to avoid the condition of a component of the critical net being in proximity to a splice. In another embodiment of the invention, where splices are utilized at overlap locations, placing a landing pad of contacts or vias at the same location as the splice.

Method for double patterning lithography

A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design

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Fremont, CA, United States of America

Anwei Liu