International Business Machines Corporation

Anuwat Saetow

Edgar Rolando Cordero

Joab Daniel Henderson

Jeffrey A Sabrowski

Adam J McPadden

David D Cadigan

Saravanan Sethuraman

William Vincent Huott

Kyu-hyoun Kim

Carlos A Fernandez

Gary A Tressler

Marc Avery Gollub

Warren Edward Maule

Timothy Jay Dell

Stephen P Glancy

Lucas W Mulkey

Divya Kumar

William Paul Hovis

Samuel R Connor

Michael Cracraft

Irving G Baysah

Briana E Foxworth

Diyanesh B Chinnakkonda Vidyapoornachary

Robert Brett Tremaine

Charles Arthur Kilmer

Anil Bindu Lingambudi

Kevin M Mcilvain

Jacob D Sloat

Nagendra K Gurram

Jeremy R Neaton

Andre A Marin

Lucus W Mulkey

In an approach to improve resolving defects within computer hardware, programs, software, or systems, embodiments pause mainline traffic and isolating interface or retention issues, and determine one or more types of errors in an event of a mainline traffic fail, wherein debug techniques are applied to fail information to resolve or further diagnose the one or more types of errors, and wherein the debug techniques are tracked and categorized. Additionally, embodiments apply corrective read actions to a detected error based on previously stored corrective actions associated with the detected error, and responsive to identifying no additional actions are required, restoring a collected system data. Further, embodiments, resume the paused mainline traffic.

Real-time error debugging

A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.

Managing heterogeneous memory resource within a computing system

A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of LLlatches connected in a chain, each LLlatch includes an Llatch and an Llatch with the Llatch having a connected output monitored for a flip. A single Ldetect circuit exclusive OR (XOR) is connected to each Llatch. An Ldetect circuit XOR tree includes an input connected to a true output of a respective Llatch in the chain. An Lclock (LCK) trigger circuit is connected to an output of the Ldetect circuit XOR tree and is shared across each of the plurality of LLlatches for correcting bit flip errors.

Implementing dynamic SEU detection and correction method and circuit

A computer-implemented method for calibrating DRAM is provided. A non-limiting example of the computer-implemented method includes reading, by a processor, system configuration information and disabling, by the processor, one or more steps in a list of calibration steps to be performed based on the system configuration information to leave a list of remaining calibration steps. Based on a determination that two or more remaining calibration steps are co-dependent, the method configures, by the processor, a single calibration step that encapsulates the co-dependent algorithm and places, by the processor, the single calibration step in a list of steps to be called. The method then provides, by the processor, the list of steps to be called.

Hardware abstraction in software or firmware for hardware calibration

A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.

Granular variable impedance tuning

A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

Implementing SEU detection method and circuit

An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Auto-disabling DRAM error checking on threshold

A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.

Memory device command-address-control calibration

An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.

Mitigation of side effects of simultaneous switching of input/output (I/O data signals

A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.

Determining timeout values for computing systems

Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

SRAM bitline equalization using phase change material

An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.

Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module

An aspect includes data backup management between volatile memory and non-volatile memory in a through-silicon via module of a computer system. Data is copied data from the volatile memory to the non-volatile memory during a refresh cycle of the volatile memory. The data is written to one or more non-volatile memory cells within the non-volatile memory prior to a next refresh cycle of the volatile memory.

Volatile and non-volatile memory in a TSV module

A method, system, and/or computer program product corrects a data error that has been caused by a break in a conductor link in a memory. A memory controller detects a line malfunction in a data bit transmission line between a first bit node and a second bit node in a memory, and then identifies a constant voltage state at the second bit node that is caused by the line malfunction. In response to determining that the constant voltage state is non-representative of the bit value intended to be transmitted from the first bit node to the second bit node, an inversion logic inverts bit values for all bits in an original bit array to create an inverted bit array, which is stored in the array of memory cells for future retrieval and re-inversion, in order to reconstruct the original bit array.

Growing community of inventors

Austin, TX, United States of America

Anuwat Saetow