Intel Corporation

Anurag Sah

Robert F Krick

Cong Quoc Khieu

Amar A Ghori

Roshan J Fernando

Adalberto Golbert

Kathakali Debnath

Yoav Hochberg

Douglas M Carean

Milind Mittal

Power down circuitry in a processor for controlling power delivered to functional units of the processor, comprising first and second power down circuits. The first power down circuit comprises a state machine having a decoded instruction as input and a control signal as output. The control signal disables a clock signal to a floating point unit (FPU) when the decoded instruction is not a floating point instruction. The second power down circuit comprises a prediction circuit that generates a predict signal when a cache access cannot occur. The predict signal disables a clock signal to a cache.

Power down scheme for idle processor components

A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

Method and apparatus for operating a single CPU computer system as a

Growing community of inventors

Aloha, OR, United States of America

Anurag Sah