Juniper Networks, Inc.

Anurag P Gupta

Song Zhang

Jean-Marc Frailong

Jeffrey Glenn Libby

Sharada Yeluri

Avanindra Godbole

Jorge Cruz-Rios

Phil Lacroute

Craig R Frink

John Keen

Weidong Xu

Harshad B Agashe

Raymond Marcelino Manese Lim

Brian C Gaudet

Raymond Lim

Deepak Goel

Jayabharat Boddu

Debashis Basu

Sanjeev Singh

Sreeram Veeragandham

David James Ofelt

Umesh Krishnaswamy

Rami Rahim

Chi-Chung Kenny Chen

Sriram Raghunathan

Srinivas Venkataraman

Jianhui Huang

Michael Beesley

Jeffrey R Zimmer

Lawrence Hui

Praveen Garapally

Edwin Su

David Talaski

Dibyendu K Sen

Srinivas Vaduvatha

Jia-Chang Wang

Srihari Shoroff

Steve W Turner

Jeffrey M DiNapoli

Paul Coelho

Norman Bristol

Pradeep S Sindhu

Abhijit Ghosh

Rajesh Nair

Oren Kerem

A network device may receive packets and may calculate, during a time interval, an arrival rate and a departure rate, of the packets, at one of multiple virtual output queues. The network device may calculate a current oversubscription factor based on the arrival rate and the departure rate, and may calculate a target oversubscription factor based on an average of previous oversubscription factors associated with the multiple virtual output queues. The network device may determine whether a difference exists between the target oversubscription factor and the current oversubscription factor and may calculate, when the difference exists, a scale factor based on the current oversubscription factor and the target oversubscription factor. The network device may calculate new scheduling weights based on prior scheduling weights and the scale factor, and may process packets received by the multiple virtual output queues based on the new scheduling weights.

Determining rate differential weighted fair output queue scheduling for a network device

An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.

Combined input and output queue for packet forwarding in network devices

A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

Use of cache to reduce memory bandwidth pressure with processing pipeline

In general, techniques of the present disclosure relate to synchronizing concurrent access to multiple portions of a data structure. In one example, a method includes, sequentially selecting a plurality of requests from a request queue, wherein at least one of the requests specifies a plurality of requested synchronization objects for corresponding candidate portions of a data structure to which to apply an operation associated with a data element. The method also includes querying one or more sets of identifiers to determine whether one or more of the requested synchronizations objects specified by the selected request are acquirable. The method also includes acquiring each of the requested synchronization objects that are acquirable. The method includes, responsive to acquiring all of the one or more requested synchronization objects, selecting a subset of the candidate portions of the data structure and applying the operation only to the selected subset of the candidate portions.

Acquisition of multiple synchronization objects within a computing device

A data read/write system receives a key associated with a data read request. The data read/write system hashes the key to obtain a first hash value and hashes the key to obtain a second hash value, where the second hash value is different than the first hash value. The data read/write system obtains a pointer from a pointer array using the first and second hash values, and uses one or more bits of the pointer and the first hash value to retrieve data from a data look-up array.

Scalable hash tables

In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.

Memory error protection using addressable dynamic ram data locations

A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.

Flexible pin allocation

Systems and methods of various embodiments provide mechanisms to support synchronous and asynchronous transactions. Distinct encodings allow an instruction to choose whether to perform any operation synchronously or asynchronously. Separate synchronous and asynchronous result registers hold the data returned in the most recent replies received for synchronous and asynchronous transaction requests, respectively. A status bit indicates whether an asynchronous transaction request is currently outstanding.

System and method for independent synchronous and asynchronous transaction requests

Output logic generates read requests using a programmable schedule that controls read bandwidth for multiple data streams and stores the read requests in a queuing device. The output logic also dequeues the read requests based on a similar programmable schedule, forwards the read requests to the memory, and reads data units from the memory based on the read requests.

Guaranteed bandwidth memory apparatus and method

Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.

System and method for efficient packet replication

Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.

Maintaining data unit order in a network switching device

Growing community of inventors

Saratoga, CA, United States of America

Anurag P Gupta