Sandisk Technologies Inc.

Sandisk 3d LLC

Anurag Nigam

Yingchang Chen

Chang Hua Siau

Gopinath Balakrishnan

Yukeun Sim

Jingwen Ouyang

Thomas Yan

Jeffrey Lee

A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.

Signal path optimization for read operations in storage devices

Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

Memory with bit line short circuit detection and masking of groups of bad bit lines

A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.

Sense amplifier with integrating capacitor and methods of operation

A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes receiving a current conducted by the word line comb, estimating a resistance of a conductive path between the word line comb and a selected word line voltage node, and generating a voltage at the selected word line voltage node based on the received current and the estimated resistance so that a voltage of the word line comb substantially equals a reference voltage.

Word line compensation for memory arrays

A non-volatile memory includes a sense amplifier that uses a reference bit line. The sense amplifier includes a first capacitor coupled to a selected bit line and a second capacitor coupled to a reference bit line. The reference capacitor compensates for displacement currents in the selected bit line during sensing. Both plates of the capacitors are utilized to cancel leakage currents. The top plates of the capacitors are precharged then discharged during a sense phase. The selected bit line capacitor is discharged based on the selected cell current and the leakage current. The amount of discharge is transferred to the bottom plate of each capacitor, followed by discharging the bottom plates. The capacitor for the selected bit line is discharged based on the leakage current. In this manner, the correction phase facilitates a compensation based on the leakage current so that the selected cell current can be determined.

Leakage current compensation with reference bit line sensing in non-volatile memory

Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

Timed multiplex sensing

Methods and apparatus are provided for reading a selected memory cell of a memory array using a sense amplifier that includes a first capacitor and a second capacitor. The selected memory cell is coupled to a bit line and a selected word line. A first noise voltage is generated on the first capacitor, and a selected memory cell voltage and a second noise voltage are generated on the second capacitor. The first noise voltage is an estimate of the second noise voltage. An output signal value is generated proportional to a difference between the selected memory cell voltage and a reference voltage, and a difference between the first noise voltage and second noise voltage. The output signal value is used to determine a data value for the selected memory cell.

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San Jose, CA, United States of America

Anurag Nigam