Globalfoundries Inc.

Arm Limited

Globalfoundries U.S. Inc.

Anurag Mittal

Mahbub Rashed

Bipul C Paul

George Jonathan Kluth

Marc Laurent Tarabbia

David C Pritchard

Randy W Mann

Werner Juengling

Manjunatha Govinda Prabhu

Kingsuk Maitra

O Sung Kwon

Xiaoqiang Zhang

Neha Nayyar

Heng Yang

Hongru Ren

Lixia Lei

Kai Sun

Nader Magdy Hindawy

Min-Hwa Chi

Peter Baars

Jagar Singh

Yanxiang Liu

Navneet Jain

Juhan Kim

Niladri Mojumder

Tuhin Guha Neogi

Pierre Malinge

Jungtae Kwon

Norman Chen

Vikrant Kumar Chauhan

Rick J Carter

Sangmoon J Kim

Jian Liu

Sandeep Puri

The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Fully depleted devices with slots in active regions

Devices with slotted active regions

A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

FDSOI semiconductor device with contact enhancement layer and method of manufacturing

At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

Antenna diode circuit for manufacturing of semiconductor devices

At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

Method, apparatus and system for using hybrid library track design for SOI technology

An electronic fuse includes a body, an anode coupled to the body, and a cathode coupled to the body. Each of the anode and the cathode includes a first line contacting the body. The first line is discontinuous along its length and includes a first portion and a second portion with a space therebetween. A second line is disposed above the first line and a plurality of vias couple the first and second lines. The first portion of the first line is coupled to a first subset of the plurality of vias and the second portion of the first line is coupled to a second subset of the vias.

Electronic fuse having a substantially uniform thermal profile

Semiconductor fuses with epitaxial fuse link regions and fabrication methods thereof are presented. The methods include: fabricating a semiconductor fuse including an anode region and a cathode region electrically linked by a fuse link region, and the fabricating including: forming, epitaxially, the fuse link region between the anode region and the cathode region, wherein the fuse link region facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region thereof. The semiconductor fuses include: an anode region and a cathode region electrically linked by a fuse link region, wherein the fuse link region includes an epitaxial structure and facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region, wherein the epitaxial structure is in at least partial crystallographic alignment with the anode region and the cathode region of the semiconductor fuse.

Semiconductor fuses and fabrication methods thereof

Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

Integrated circuit with semiconductor fin fuse

Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.

Forming a low votage antifuse device and resulting device

An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates.

Embedded selector-less one-time programmable non-volatile memory

A method includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result.

Modeling memory cell skew sensitivity

Methods for forming a variable fin FinFET cell wherein a plurality of fins is formed above a substrate, a portion of a fin is removed, forming a fin tip, a first area of a gate oxide layer is formed above the fin tip, and a second area of the gate oxide layer is formed above at least a remaining portion of the plurality of fins, wherein the first area is thicker than the second area.

Forming finfet cell with fin tip and resulting device

A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.

Power rail layout for dense standard cell library

An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.

Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product

An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices.

Growing community of inventors

Wappingers Falls, NY, United States of America

Anurag Mittal