Oracle International Corporation

Synopsys, Inc.

Anurag Garg

Douglas Ray Cosby

Harold Pilo

Byron Kevin McKenzie

Rahul R Kamath

Jack Randall Smiley

James Charles McCausland

Shishir Kumar

Matthew Lawrence Lontchar

Jeffrey Leon Woodard

Randy Lee Haben

John Edward Barth, Jr

Narayan Madhavan Nayar

Peter Kwang Lee

Mark Allen Brieden

Michael Lee

Sanjiv Kainth

A method and circuit are provided for maintaining an operating voltage on a selected column with a plurality of bitcells in a memory when writing to the selected column. The method includes during an active write operation to the selected column, implementing an NMOS transistor NC to allow a bitcell-supply self-discharge (BSSD) to occur on the selected column, wherein the BSSD occurs by connecting a first drain voltage to an operating voltage connection of the selected column via the NMOS transistor NC to allow discharge of the operating voltage connection while limiting over-discharge of the selected column. The method further includes a PMOS select transistor PS to connect a second drain voltage to the operating voltage connection of the unselected column.

Memory with hybrid write assist scheme

Techniques for modifying a query based on a data index of nodes in a data set are disclosed. A system modifies queries based on query terms associated with indexed data. The system modifies queries to include query terms based on indexed data or to obtain values for query terms that are not associated with indexed node properties. The system adds query terms, that reference indexed data, to a query in response to determining that none of a query's terms reference indexed data. The system derives values for query terms that are not associated with indexed node properties using a logical or mathematical formula. The system traverses parent nodes of a child node to identify values for query terms that are not associated with the child node in a data index, but are inherited from a parent node.

Index-based modification of a query

A data synchronization system accesses a plurality of data sets. The system receives a subscription from a third application to a first data set of a first application. When the system receives a notification of an update to a first item of the first data set, and determines via a mapping within the subscription, a value to use as a version of the first field for a corresponding item of a third data set. When the system receives input overriding the first mapping to determine values from a first field of the second data set, the system stores override metadata indicating the second data set is a data source for the third data set. After the mapping is overridden, when receiving a notification of an update to the second data set, the system triggers a modification to the first corresponding item based on the update to the second corresponding item.

Multi-master management of hierarchical master and reference data

Techniques for modifying hierarchal-structured data of one hierarchal data structure based on a modification to another hierarchal data structure are disclosed. A system determines that a modification has been made, or is requested to be made, to a particular hierarchal data structure. The system analyzes a set of rules to determine whether the modification of the hierarchal data structure triggers another modification to an additional hierarchal data structure. The additional hierarchal data structure includes different nodes, or nodes arranged in a different hierarchal structure, than the particular hierarchal data structure. The system modifies the additional hierarchal data structure based on the rule. The modification of the additional hierarchal data structure is different than the modification to the particular hierarchal data structure.

Hierarchal data structure modification

A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.

Memory with external clock synchronized operation

A data management system receives updates to records of a source dimension. Some records of the source dimension reference target dimensions. The data management system identifies template records from existing records in the source dimension for modeling changes to connections with the target dimensions based on the updated records in the source dimension. The template records are discovered using rules-driven processes, AI-driven processes, or a serial or parallel hybrid processes including rules and AI. These processes use ancestor information from the updated records to find best-matching template records. The rules-driven processes additionally rely on matching fields, and the AI-driven processes additionally rely on vector embeddings and optionally clustering. Updates are made to the target records in the target dimensions, including any roll-up structures indicated for data propagation, identified using the template records, and downstream applications using the target records may consume the updates.

Rules driven application synchronization by automatically detecting different template nodes for different synchronization targets

A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Interface level-shifter dual-rail memory architecture

A data management system determines that an updated thesaurus entry does not exist for a value of a record. The data management system generates a prompt to discover a set of synonyms and/or acronyms for the value by substituting a placeholder in a thesaurus prompt template with the value. The thesaurus prompt template includes a request that specifies an output format. A large language model is prompted with the prompt to generate a set of resulting values. The data management system causes display of the value, resulting value(s) that have not been approved, and an option to mark any of the resulting value(s) as approved. Based at least in part on receiving a selection of the option that marks at least one resulting value as approved, the data management system modifies a thesaurus entry for the value to indicate approval. The thesaurus entry is used to locate the record in response to a query.

Intelligently expanding search results ahead-of-time

A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is in the testing mode of operation the circuit, receiving test data obtained from read address signals to represent a test state for the bit cells of the memory.

At-speed synchronous write-through operation for testing two-port memory

A data hierarchy including individual data nodes may be used to represent a wide variety of data collections. Requests to change or add nodes in the data hierarchy may be received from many different sources over time. Instead of considering these change requests individually, an interface allows a plurality of change requests to be consolidated together into a single consolidated request. The consolidated request may be displayed in an interface such that changes from each of the original requests may be displayed together in an interface so that a cumulative effect of each of the change requests may be considered before the data changes are committed to the underlying data structure. The consolidated request may maintain links and update underlying data objects representing each of the original requests to provide a record of actions related to the consolidated request.

Consolidating change requests in data hierarchies

A database manager is disclosed that retrieves database records having binary encoded data from a database and instantiating objects in an in-memory database. Binary encoding compresses data, allowing many subrecords to be stored a single blob field of a database record. Retrieving chunks from storage reduces transfer time by reducing the size of data and the number of operations needed to retrieve all the subrecords. The database manager receives database access requests from a database application. Changes made to the database objects and committed by the application are written back to the persistent database as versioned delta records. In a subsequent session, loading the database from storage includes first loading the most recent snapshot record, then applying changes to the data stored in delta records. The changes stored in the delta records are applied to the data in the snapshot record in the order in which they were made.

Storing and versioning hierarchical data in a binary format

Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Power supply tracking circuitry for embedded memories

Techniques for managing requests to modify a data set at future times are disclosed. The system receives a request to modify the data set at a future time, such as in a future time window. The system generates a representation of the data set at the future time. The system determines the future state of the data set based on the current state of the data set and requested future modifications to the data set. The system determines whether a conflict exists between the request to modify the data set at the future time and another scheduled request to modify the data set at the future time. Based on determining whether a conflict exists, the system performs one or more of scheduling the request to modify the data set at the future time and performing a remediation action to address the conflict.

Future transaction processing

A browser is disclosed that provides for browsing a hierarchical dataset including potentially millions of nodes. The hierarchical dataset may be located on a machine that is remote to the machine hosting the browser. Through selective, intelligent fetching and local cache management of sparse portions of the hierarchical dataset, the browser provides consistent and predictable response times for displaying a randomly-selected node in the context of proximate nodes in the hierarchy.

Growing community of inventors

Cupertino, CA, United States of America

Anurag Garg