Barefoot Networks, Inc.

Juniper Networks, Inc.

Intel Corporation

Anurag Agrawal

Changhoon Kim

Jeongkeun Lee

Julianne Zhu

Patrick W Bosshart

Philip A Thomas

Michael Feng

Yi Li

Xiaozhou Li

Remy Chang

Masoud Moshref Javadi

Michael Gregory Ferrara

Jay Evan Scott Peterson

Alain Loge

Antonin Mathieu Bas

Chaitanya Kodeboyina

Steven Licking

Parag Dattatraya Bhide

Song Zhang

Srivathsa Dhruvanarayan

John Andrew Fingerhut

Xiaoyan Ding

Yan Wang

Kireeti Kompella

Jean-Marc Frailong

Gunes Aybay

Rong Pan

Ethan M Spiegel

Fuguang Shi

Ashutosh Agrawal

Sathish M Shenoy

Robert Li

Georgios Nikolaidis

Jeremias Blendin

Sathish Shenoy

Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

Path selection for packet transmission

Examples described herein relate to a network element comprising an ingress pipeline and at least one queue from which to egress packets. The network element can receive a packet and generate a congestion notification packet at the ingress pipeline to a sender of the packet based on detection of congestion in a target queue that is to store the packet and before the packet is stored in a congested target queue. The network element can generate a congestion notification packet based on a queue depth of the target queue and likelihood the target queue is congested. The likelihood the queue is congested can be based on a probabilistic function including one or more of Proportional-Integral (PI) or Random Early Detection (RED). The network element can determine a pause time for the sender to pause sending particular packets based at least on a time for the target queue to drain to a target level.

Congestion management techniques

Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

Messaging between remote controller and forwarding element

A method of multicasting packets by a forwarding element that includes several packet replicators and several egress pipelines. Each packet replicator receives a data structure associated with a multicast packet that identifies a multicast group. Each packet replicator identifies a first physical egress port of a first egress pipeline for sending the multicast packet to a member of the multicast group. The first physical egress port is a member of LAG. Each packet replicator determines that the first physical egress port is not operational and identifies a second physical port in the LAG for sending the multicast packet to the member of the multicast group. When a packet replicator is connected to the same egress pipeline as the second physical egress, the packet replicator provides the identification of the second physical egress port to the egress pipeline to send the packet to the multicast member. Otherwise the packet replicator drops the packet.

Link aggregation group failover for multicast

Some embodiments provide a method for an ingress packet processing pipeline of a network forwarding integrated circuit (IC). The ingress packet processing pipeline is for receiving packets from a port of the network forwarding IC and processing the packets to assign different packets to different queues of a traffic management unit of the network forwarding IC. The method receives state data from the traffic management unit. The method stores the state data in a stateful table. The method assigns a particular packet to a particular queue based on the state data received from the traffic management unit and stored in the stateful table.

Using stateful traffic management data to perform packet processing

Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

Forwarding element data plane performing floating point computations

Forwarding element data plane with computing parameter distributor

Some embodiments provide novel circuits for augmenting the functionality of a data plane circuit of a forwarding element with one or more field programmable circuits and external memory circuits. The external memories in some embodiments serve as deep buffers that receive through one or more FPGAs a set of data messages from the data plane (DP) circuit to store temporarily. In some of these embodiments, one or more of the FPGAs implement schedulers that specify when data messages should be retrieved from the external memories and provided back to the data plane circuit for forwarding through the network. For instance, in some embodiments, a particular FPGA can perform a scheduling operation for a first set of data messages stored in its associated external memory, and can direct another FPGA to perform the scheduling operation for a second set of data messages stored in the particular FPGA's associated external memory. Specifically, in these embodiments, the particular FPGA determines when the first subset of data messages stored in its associated external memory should be forwarded back to the data plane circuit to forward to data messages in the network, while directing another FPGA to determine when a second subset of data messages stored in the particular FPGA's external memory should be forwarded back to the data plane circuit.

Augmenting data plane functionality with field programmable integrated circuits

Some embodiments provide novel circuits for recording data messages received by a data plane circuit of a forwarding element in an external memory outside of the data plane circuit. The external memory in some embodiments is outside of the forwarding element. In some embodiments, the data plane circuit encapsulates the received data messages that should be recorded with encapsulation headers, inserts into these headers addresses that identify locations for storing these data messages in a memory external to the data plane circuit, and forwards these encapsulated data messages so that these messages can be stored in the external memory by another circuit. Instead of encapsulating received data messages for storage, the data plane circuit in some embodiments encapsulates copies of the received data messages for storage. Accordingly, in these embodiments, the data plane circuit makes copies of the data messages that it needs to record.

Recording in an external memory data messages processed by a data plane circuit

Growing community of inventors

Santa Clara, CA, United States of America

Anurag Agrawal