Sun Microsystems, Inc.

Apple Inc.

Anup S Mehta

Shaishav A Desai

Edgardo F Klass

Tse-Yu Yeh

Daniel C Murray

Po-Yung Chang

Gregg K Tsujimoto

Arjun P Chandran

Claude R Gauthier

Chaim Nmi Amir

Farzad Chehrazi

Devendra N Tawari

Ashutosh K Das

Betty Y Lau

Srinivasa Gopaladhine

In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted.

IR(voltage) drop analysis in integrated circuit timing

In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.

Efficient encoding for detecting load dependency on store with misalignment

In the Retirement Payload Array (RPA) of a microprocessor, the signal 'READ' is logically combined with the primary clock signal 'CLK' in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or &#x201c;glitch&#x201d; will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Modified glitch latch for use with power saving dynamic register file structures

In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal 'ADVANCE POINTER' from the Instruction Retirement Logic (IRL) of the Instruction Scheduling Unit (ISU) is utilized to provide conditional read RPA signals. Consequently, according to the invention, a read of the RPA is completed only if it is determined that the read word line being read in the current cycle is not the same read word line that was read in the previous cycle.

Modified retirement payload array

A method and apparatus that dynamically control an amount of offset current generated by a keeper device are provided. Further, a method and apparatus that use a temperature-controlled keeper device to dynamically optimize an evaluation performance of a dynamic circuit are provided. In particular, when IC temperature is relatively high, i.e., there is increased current leakage in the dynamic circuit, an amount of offset current output by the temperature-controlled keeper may be increased, thereby preventing a dynamic node of the dynamic circuit from being discharged, or otherwise adversely affected, by the increased current leakage. Alternatively, when the IC temperature is relatively low, i.e., there is decreased current leakage in the dynamic circuit, the amount of offset current output by the temperature-controlled keeper may be decreased, thereby ensuring that the offset current is not so large that it severely degrades the evaluation performance.

Dynamic circuitry with on-chip temperature-controlled keeper device

A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.

Multiple discharge capable bit line

An electronic circuit has a register connected to a sense amplifier via a bitline (the sense amplifier has a primary precharge circuit), and a secondary precharge circuit also connected to the bitline. For bitlines that are relatively long, the secondary precharge circuit is located at a distal end of the bitline with respect to the sense amplifier. The secondary precharge circuit initially pulls up the voltage of the bitline, and the primary precharge circuit in the sense amplifier completes the precharging of the bitline. The secondary precharge circuit includes a cascode transistor coupled to the bitline via a feedback circuit. The feedback circuit is enabled during the precharge phase, when the bitline is discharged below a preset threshold. The threshold of the secondary precharge circuit can be set such that any skew between the precharge pulses of the secondary precharge circuit and the sense amplifier does not affect the falling bitline during the sense amplifier evaluate phase. Because of the initial surge of precharge from the secondary precharge circuit, the bitline is completely precharged in a shorter cycle time, allowing the sense amplifier to be operated at higher frequencies.

Secondary precharge mechanism for high speed multi-ported register files

A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

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Fremont, CA, United States of America

Anup S Mehta