Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Anup P Jose

Amir Amirkhany

Younghoon Song

Gaurav Malhotra

Mohamed N Elzeftawi

Ali Fazli Yeknami

Mohammad Hekmat

Moonsang Hwang

Valentin Abramzon

Sam Ray

An adaptation engine included in a receiver of a serial data link, including at least one processor configured to: receive an error signal generated by an error slicer included in a decision feedback equalizer (DFE) and a data signal generated by a data slicer included in the DFE, perform a first iterative adaptation process corresponding to the AFE by adjusting a gain of the AFE based on the error signal and the data signal, and perform a second iterative adaptation process corresponding to the AFE by adjusting an degeneration resistance of a degeneration resistor included in the AFE based on the error signal and the data signal.

Adaptive AFE calibration techniques

An analog front end (AFE) circuit including: a continuous time linear equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit including: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; the second output of the feedback circuit is connected to a first input of the TIA.

Continuous time linear equalization (CTLE) feedback for tunable DC gain and mid-band correction

A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

Systems and methods for transition encoding compatible PAM4 encoding

A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1≤M≤Z, determining an Errorusing the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the Error. The adjusting of the input voltage may include generating a modified voltage V, whereinand each of A and B is determined using Σsign(Error).

Multi-pixel collective adjustment for steady state tracking of parameters

A receiver for a serial data link, including an analog front end (AFE) including a continuous-time linear equalizer (CTLE) configured to receive an input signal from a transmitter, the CTLE including a first output node; a second output node; a plurality of programmable tail current sources configured to adjust a direct current (DC) offset between the first output node and the second output node; and a calibration circuit including: a slicer configured to output a difference between a first average output voltage corresponding to the first output node and a second average output, voltage corresponding to the second output node; and a calibration counter configured to increment or decrement an offset count based on the difference, wherein the plurality of programmable tail current sources are adjusted based on a value of the offset count.

Real-time DC-balance aware AFE offset cancellation

A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

Clock data recovery (CDR) with multiple proportional path controls

A circuit. In some embodiments, the circuit includes: a drive circuit having an output and including: a pre-emphasis circuit; and an output stage connected to an output of the pre-emphasis circuit. The pre-emphasis circuit may be configured to generate, during a first interval of time, a pre-emphasized signal. The output stage may be configured to produce, at the output of the drive circuit, a constant signal based on the pre-emphasized signal during the first interval of time, and to disconnect the pre-emphasis circuit from the output of the drive circuit during a second interval of time, the second interval of time beginning at the end of the first interval of time.

Voltage mode pre-emphasis with floating phase

A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.

Estimation of pixel compensation coefficients by adaptation

A system and method for sensing drive current in a pixel. In some embodiments, the system includes: a first pixel, a second pixel, a differential sensing circuit, a reference current source, and a control circuit. The differential sensing circuit may have a first input, a second input, and an output, the first input being connected to a node at which a reference current generated by the reference current source is subtracted from a first pixel current, the first pixel current including a current generated by the first pixel. The second input may be configured to receive a second pixel current, the second pixel current including a current generated by the second pixel. The output may be configured to produce an output signal based on a difference between a current received at the first input and a current received at the second input.

Fully differential front end for sensing

A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.

Correlated double sampling pixel sensing front end

A device includes a segmented pull-up current source circuit including a first plurality of transistors, a segmented pull-down current source circuit including a second plurality of transistors, a comparator circuit configured to compare an output voltage level at the output of the device with a target voltage level and generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, the first plurality of AND gate circuits and a second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control an operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output.

High-efficiency piecewise linear column driver with asynchronous control for displays

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Hybrid half/quarter-rate DFE

A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Average and decimate operations for bang-bang phase detectors

A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.

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San Jose, CA, United States of America

Anup P Jose