Intel Corporation

Anup Mohan

Kshitij Arun Doshi

Harshad S Sane

David M Durham

Ravi L Sahita

Mohan J Kumar

Baiju V Patel

Ravishankar Iyer

Mark A Schmisseur

Michael Lemay

Andrew J Herdrich

Sara S Baghsorkhi

Jr-Shian Tsai

Vadim Sukhomlinov

Alexander Bachmutsky

Mingqiu Sun

Ian M Steiner

Jeffrey D Chamberlain

Nilesh K Jain

Eric Dahlen

Mohammad R Haghighat

Mingwei Zhang

Amin Firoozshahian

Yeluri Raghuram

Dmitry Babokin

Anil Rao

Krishna Bhuyan

Leeor Peled

Areg Melik-Adamyan

Teck Joo Goh

Michael Prinke

Wenyong Huang

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

Function as a service (FaaS) system enhancements

A computing system includes a memory controller having a plurality of bypass parameters set by a software program, a thresholds matrix to store threshold values selectable by the plurality of bypass parameters, and a bypass function to determine whether a first cache line is to be displaced with a second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of a processor core and the cache from a second memory.

Method of managing multi-tier memory displacement using software controlled thresholds

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Milpitas, CA, United States of America

Anup Mohan