Xilinx, Inc.

Anup Kumar Sultania

Fan Zhang

Chaithanya Dudha

Sabyasachi Das

Guenter Stenz

Chun Zhang

Krishna Garlapati

Nithin Kumar Guggilla

Yau-Tsun Steven Li

Govinda Keshavdas

E Syama Sundara Reddy

Register pull-out for sequential circuit blocks may include determining, using computer hardware, a net of a circuit design having a driver that is a macro circuit block driving a plurality of loads and determining, using the computer hardware, a placement difficulty of the net based upon a type of the driver and number and type of the plurality of loads. In response to determining that the placement difficulty of the net exceeds a threshold placement difficulty, the computer hardware is capable of modifying the circuit design by pulling a register from the driver to a location on a device external to the driver and changing internal logic of the driver based upon the pulled register.

Register pull-out for sequential circuit blocks in circuit designs

Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.

Partitioning memory blocks for reducing dynamic power consumption

Disclosed approaches of determining an estimated glitch toggle rate at an output of a logic circuit include inputting functional static probabilities of combinations of states of the plurality of inputs and a generated glitch toggle rate of the logic circuit. Each functional static probability indicates a probability of the states of the inputs of the combination. For each input of the plurality of inputs to the logic circuit, a Boolean Difference Function (BDF) of the input is generated. A maximum glitch rate, which is the estimated glitch toggle rate, is determined based on the generated glitch toggle rate and the functional static probabilities associated with selected combinations of states of the BDF.

Estimation of power consumed by combinatorial circuitry

A method relating generally to simulation is disclosed. In such a method, a first signal input and a second signal input are provided to a multiple clock domain object. The first signal input is for a first clock domain. The second signal input is for a second clock domain. The first clock domain is associated with a first frequency, and the second clock domain is associated with a second frequency different from the first frequency. The first signal input and the second signal input are converted to a common multiple clock frequency. A signal output is obtained from the multiple clock domain object responsive to the common multiple clock frequency. Switching activity is estimated for the multiple clock domain object. An output estimate associated with the switching activity estimated is output.

Switching activity estimation for a multi-clock domain for power consumption estimation

Vectorless dynamic power estimation for a circuit design may include forming, using a processor, a complex basic element within the circuit design, determining, using the processor, initial toggle rates for basic elements within the circuit design, and determining, using the processor, an initial toggle rate for the complex basic element. Vectorless dynamic power estimation further may include generating, using the processor, final toggle rates by updating the initial toggle rates according to a control signal analysis and calculating, using the processor, dynamic power dissipation for the circuit design using the final toggle rates.

Vectorless dynamic power estimation for sequential circuits

Processing a circuit design for implementation on a target device includes, for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. The connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

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Livingston, AL, United States of America

Anup Kumar Sultania