Alpha & Omega Semiconductor Corporation

United Silicon Carbide, Inc.

Other

Vishay-siliconix

Siliconix Incorporated

Fairchild Semiconductor Corporation

United Silicone Carbide, Inc.

Alpha To Omega Semiconductor, Inc.

Aplha and Omega Semiconductor Incorporated

Anup Bhalla

Sik Lui

Hamza Yilmaz

Madhur Bobde

Lingpeng Guan

Daniel Ng

Xiaobin Wang

John Chen

Hong Chang

Ji Pan

Yueh-Se Ho

Yi Qiang Su

TingGang Zhu

François Hébert

Tiesheng Li

Jun Lu

Moses Ho

Yeeheng Lee

Sung-Shan Tai

Jongoh Kim

Yan Xun Xue

Sung-Po Wei

Jun Hu

Wilson Ma

Kai Chieh Liu

Yongping Ding

Zhongda Li

Ping Huang

Xiaotian Zhang

Jacek Korec

Leeshawn Luo

Daniel S Calafut

Mike F Chang

Leonid Fursin

Wenjun Li

Il Kwan Lee

Lingping Guan

Xiaorong Shi

Tao Feng

Dorman C Pitzer

Yu Wang

Yingying Lou

Lei Shi

Wei D Wang

Peter Alexandrov

Wayne F Eng

Francois Hebert

Ming Sun

Xiao Meng Zhang

Allen Chang

John Amato

Sanjay Havanur

Limin Weng

Xueqing Li

David Grey

Hao Zhang

Harsh Naik

Fei Wang

Y Mohammed Kasem

Praveen Muraleedharan Shenoy

Eddy Tjhia

Bosco Lan

Chang-Sheng Chen

Man Sheng Hu

Madhur Bodbe

Francisco Astrera Sudario

Lee Shawn Luo

Lingpeng Guann

Ji Pang

Yeeherg Lee

Kal Liu

Kenny Man Sheng Hu

Domon Pitzer

Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

Reusable wide bandgap semiconductor substrate

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Sawtooh electric field drift region structure for planar and trench power semiconductor devices

A chip stack assembly uses a monolithic metallic multilevel connector to both join connections on at different heights on the top sides at the of the chips, and to provide a large, robust connection surface on top of top of the assembly.

Double-sided chip stack assembly

A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.

MOS device with island region

This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Device structure and manufacturing method using HDP deposited source-body implant block

Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant.

Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a 'Gap Filler' layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The 'Gap Filler' layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

Nano-tube MOSFET technology and devices

This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances

A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.

MOSFET device and fabrication

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Nanotube semiconductor devices

A nitride-based Schottky diode includes a nitride-based semiconductor body, a first metal layer forming the anode electrode, a cathode electrode in electrical contact with the nitride-based semiconductor body, and a termination structure including a guard ring and a dielectric field plate. In one embodiment, the cathode electrode is formed on the front side of the nitride-based semiconductor body, in an area away from the anode electrode and the termination structure. In another embodiment, the dielectric field plate includes a first dielectric layer and a recessed second dielectric layer. In another embodiment, the dielectric field plate and the nitride-based epitaxial layer are formed with a slant profile at a side facing the Schottky junction of the Schottky diode. In another embodiment, the dielectric field plate is formed on a top surface of the nitride-based epitaxial layer and recessed from an end of the nitride-based epitaxial layer near the Schottky junction.

Vertical gallium nitride Schottky diode

Fabricating a semiconductor device includes: forming a first gate trench and a second gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the first gate trench to form a first gate and depositing gate material in the second gate trench to form a second gate; forming a body; forming a source; forming an active region contact trench that extends through the source and the body, and a gate contact trench within the second gate; forming an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; and disposing a first electrode within the active region contact trench and a second electrode within the gate contact trench.

Device and fabrication of MOS device with island region

A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Methods for fabricating anode shorted field stop insulated gate bipolar transistor

Growing community of inventors

Santa Clara, CA, United States of America

Anup Bhalla