Freescale Semiconductor,inc.

Anuj Singhania

Anis Mahmoud Jarrar

Milind P Padhye

Arijit Dutta

Noah Bamford

Bryan T Weston

A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level.

Multiple function power domain level shifter

A method of operating a circuit, including operating in a first mode, wherein in the first mode, a first power domain operates in an active power mode and a second power domain operates in an active power mode, wherein in the first mode, a first set of at least one terminal of a first circuit of the first power domain are coupled to a second set of at least one terminal of a second circuit of the second power mode via an isolation circuit for providing signals from the first circuit to the second circuit, is provided. The method further includes operating the circuit in a second mode, wherein in the second mode, the first power domain operates in a power gated mode and a second power domain operates in an active power mode.

Management of power domains in an integrated circuit

A method for performing a voltage drop analysis in a logic circuit that takes into consideration voltage drop&#x2014;current drain dependency. The voltage drop analysis helps in accurately estimating power requirements of the logic circuit, designing optimal power grids and performing accurate static timing analysis for the logic circuit. The logic circuit has a plurality of gates. The method generates polynomial models for the power consumption, delay and transition time of each gate in the logic circuit. Thereafter, the polynomial models are solved to determine the supply voltage available at each gate of the logic circuit. The supply voltage, thus determined, is used to perform voltage drop analysis.

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Austin, TX, United States of America

Anuj Singhania