Honeywell International Inc.

Ademco Inc.

Anuj Kohli

Romney R Katti

James L Tucker

David Mulhouse

Liliana Reategui

Robert D Juntunen

Mohammad Aljabari

Michael S Liu

Tracy L Lentz

Jiri Sapak

David K Nelson

Daniel Becvar

Hyunki Kim

Harry H L Liu

Jesus Omar Ponce

Walter W Heikkila

Joe G Guimont

A system for detection of equipment connections to a thermostat. The thermostat has one or more terminals with a one-to-one connection to one or more loads respectively of heating, ventilation and/or air conditioning equipment, and one or more terminals with a one-to-one connection to electrical power. One or more detectors are connected one-to-one to each of the one or more terminals, respectively, for connection to the one or more loads, and the one or more connections to the electrical power. Each detector is connected to a processor. Each detector is configured to provide a signal to the processor relative to a corresponding terminal indicating a status of a connection of the terminal to a load or to the electrical power.

Detection of HVAC equipment wired to a thermostat

A device for detecting a wire configuration connecting a thermostat and HVAC equipment includes fan controller circuitry, AC controller circuitry, switching circuitry, and processing circuitry. The fan controller circuitry is configured to operate a fan unit of the HVAC equipment using a G pin in a first wire configuration and using a K pin in a second wire configuration. The AC controller circuitry is configured to operate an AC unit of the HVAC equipment using a Y pin in the first wire configuration and the K pin in the second wire configuration. The switching circuitry is configured to refrain from electrically coupling the Y pin and the K pin in response to a deactivation signal. The processing circuitry is configured to determine the HVAC equipment is in the first wire configuration in response to determining the AC controller circuitry receives power while outputting the deactivation signal to the switching circuitry.

Thermostat wire detection

A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.

Anti-tampering devices and techniques for magnetoresistive random access memory

A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.

Power cycling power on reset circuit for fuse initialization circuitry

An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer.

Magnetoresistive random access memory (MRAM) die including an integrated magnetic security structure

A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.

Magnetoresistive random access memory (MRAM) package including a multilayer magnetic security structure

A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.

Tamper-resistant MRAM utilizing chemical alteration

A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.

Growing community of inventors

Apple Valley, MN, United States of America

Anuj Kohli