Globalfoundries Inc.

Globalfoundries U.S. Inc.

Anuj Gupta

Bipul C Paul

Joseph Versaggi

Xusheng Kevin Wu

Randy W Mann

Sonia Ghosh

Sandeep Puri

Joe A Versaggi

One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.

Memory cells with vertically overlapping wordlines

The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

Circuit structure and method for resistive RAM with self aligned contacts in zero-via layer

The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.

Twisted wordline structures

Structures for a bitcell of a non-volatile memory and methods of fabricating such structures. A field-effect transistor of the bitcell includes a gate having gate electrodes that are arranged in a four contacted (poly) pitch layout. An interconnect structure is arranged over the field-effect transistor, and a memory element arranged in the interconnect structure. The memory element is connected by the interconnect structure with the field-effect transistor.

Bitcells for a non-volatile memory device

Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

Wordline strapping for non-volatile memory elements

Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

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Sunnyvale, CA, United States of America

Anuj Gupta