Synopsys, Inc.

Nvidia Corporation

Intel Corporation

Anubhav Sinha

Amit D Sanghani

Abhijeet Samudra

Ramalingam Kolisetti

Milind Bhaiyyasaheb Sonawane

Ajay Nagarandal

Emil I Gizdarski

Shantanu Sarangi

Sreejit Chakravarty

Karthikeyan Natarajan

Fei Su

Mahmut Yilmaz

Rakesh Reddy Kandula

Salvatore Talluto

Brian Archer

Vishal Agarwal

Terrence Huat Hin Tan

Puneet Gupta

Amit Gopal M Purohit

Satya Puvvada

Pavan Kumar Datla Jagannadha

Wei Ming Lim

Dheepakkumaran Jayaraman

Naresh Thakur

Milin Kaushik Raijada

Luis M Cruz

Bartosz Grzegorz Gajda

Yongkang Hu

Sai Manish Rao Marru

Sahil Soni

Saransh Nagaich

Hemasagar Babu Reddy

Sudheer V Badana

Akshay Kumar Gupta

Amit Kapatkar

Kranthi Kandula

Adithya B S

Jatin Verma

Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet.

Device under test synchronization with automated test equipment check cycle

A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.

Testable time-to-digital converter

Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

Using scan chains to read out data from integrated sensors during scan tests

Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

Deterministic data latency in serializer/deserializer-based design for test systems

An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.

High-speed functional protocol based test and debug

Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Packetized power-on-self-test controller for built-in self-test

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Test architecture for die to die interconnect for three dimensional integrated circuits

In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

Dynamic independent test partition clock

A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Global low power capture scheme for cores

Growing community of inventors

Hyderabad Telangana, India

Anubhav Sinha