Qualcomm Incorporated

Anubhav Mishra

Manu Gulati

Alon Naveh

Nitin Makhija

Mahadevamurty Nemani

Adarsh Baraka Ravi

Arun Sukheja

Autonomously managing core cluster frequencies using performance statistics in processor devices is disclosed herein. In some aspects, a cluster power management circuit of a processor device collects Activity Management Unit (AMU) statistics for multiple processor cores for each of one or more frequency operating points over a time interval. Based on the AMU statistics, the cluster power management circuit generates a performance model representing processor performance as a function of frequency, and uses the performance model and a power consumption measurement to generate an energy-per-instruction (EI) model representing energy per instruction as a function of frequency. The cluster power management circuit then generates an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency, and identifies a target frequency operating point based on the advantage model.

Autonomously managing core cluster frequencies using performance statistics in processor devices

This application is directed to power management at a processor system having a plurality of domains. Power samples are collected from the domains and combined to generate a system temperature profile including a temporal sequence of system temperature values. When the system temperature profile satisfies a first criterion, it is determined in real time whether a respective system temperature value of the system temperature profile satisfies a second criterion or a third criterion. In accordance with a determination that the respective system temperature value satisfies the second criterion, a power management engine determines power budgets of the domains on a firmware level and enables operations of the domains according to the power budgets. In accordance with a determination that the respective system temperature value satisfies the third criterion, a subset of domains are selected to apply a respective power throttling action directly on a hardware level.

Dynamic power management for SoC-based electronic devices

An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

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Fremont, CA, United States of America

Anubhav Mishra