Synopsys, Inc.

Antony Fan

Mayukh Bhattacharya

Huiping Huang

Mihir Sherlekar

Yo Ng Zhou

A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.

Fast and scalable methodology for analog defect detectability analysis

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

Guiding sample size choice in analog defect or fault simulation

A system and a method for performing circuit simulation on a integrated circuit design that is represented by a hierarchical netlist. The system and method utilize, in one embodiment, an event driven simulator that divides or &ldquo;cuts&rdquo; along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into their Thevenin equivalents. Once a Thevenin equivalent is computed, matrix computations are used to compute the cut node voltages and sensitivity vectors may be used to then determine the internal node voltages. This is done for each event. In the event driven example, a group of leaf cells are identified that are touched by a given event. This group is then cut based on the hierarchical boundaries of the input netlist. The system maintains dynamic node voltages across the entire netlist and also maintains instance specific dynamic information for each cell. However, static information for a given cell is shared for each cell instance thereby reducing memory resources required to perform simulation for input hierarchical netlists that contain repeated cell instances. The present invention provides an accurate voltage and current simulation while requiring reduced memory resources for hierarchical netlists that contain repeated cell instances.

System and method for simulation of an integrated circuit design using a hierarchical input netlist and divisions along hierarchical boundaries thereof

Growing community of inventors

Mountain View, CA, United States of America

Antony Fan