Psemi Corporation

Murata Manufacturing Co., Ltd.

Antony Christopher Routledge

Satish Kumar Vangara

Gregory Szczeszynski

Xiaowu Sun

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage Vapplied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that Vis adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V; connecting to the gate of the power FET allows Vto be directly set.

Accurate reduced gate-drive current limiter

Circuits and methods for selectable conversion ratio power converters that include low-dropout (LDO) power supplies adapted to select voltage inputs based on the selected conversion ratio while achieving high efficiency. The LDO power supplies limit current through power FETs of power converters, thereby mitigating or eliminating potentially damaging events. In some embodiments, first and second full gate-drive LDOs have 'wired-OR' outputs which may power a target circuit such as a pre-driver (and optionally, a level-shifter) coupled to the gate of a power FET. In some embodiments, first and second reduced gate-drive LDOs have “wired-OR” outputs that may power a final driver coupled to the gate of a power FET. Some embodiments have dual full gate-drive LDOs that power a target circuit such as a pre-driver (and optionally, a level-shifter), while dual reduced gate-drive LDOs that power a final driver coupled to the gate of the power FET.

Reduced gate drive for power converter with dynamically switching ratio

Circuits and methods to mitigate or eliminate potentially damaging events (e.g., damaging current spikes from in-rush current, charge transfer current, short circuits, etc.) in DC-DC power converters. Embodiments enable dynamic switching of conversion ratios in reconfigurable power converters while under load without turning off the power converter circuitry or suspending switching of the charge pump power switches. Embodiments selectively increase the ON resistance, R, for at least some power FETs in a power converter by actively controlling the driver voltage to the gates of the power FETs. During normal operation, the power FET driver voltage may be set to overdrive the FET gate to lower Rto a desired level that allows high current flow. For other scenarios, the power FET driver voltage may be reduced so as to increase Rwhile ON and thus impede current flow to provide protection against potentially damaging events.

Dynamic division ratio charge pump switching

Circuits and methods for protecting the switches of charge pump-based power converters from damage if a Vshort circuit event occurs and/or if Vfalls rapidly with respect to Vor V. A general embodiment includes a VDetection Block coupled to the core block of a power converter. The VDetection Block is coupled to Vand to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in Vduring the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a VDetection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of Vto the power converter. The VDetection Block is coupled to V, and to Vor Vin some embodiments, and to a control circuit to that disables operation of an associated converter circuit.

In-rush current protected power converter

Circuits and methods for limiting excessive current in circuits (such as step-up DC-to-DC converter circuits) in which very low ohmic FETs (VLOFETs) are used in circuit pathways that are subjected to startup in-rush current. Embodiments include a current mirror driver circuit that can be coupled to the gates of a VLOFET to form a current mirror that limits current flow through the VLOFET. The current mirror driver circuit provides for pulsed operation so that a coupled VLOFET still toggles between an OFF state and a current limited mode, particularly during a startup period. By using the current mirror driver circuit in conjunction with VLOFETs in circuit pathways that are subjected to startup in-rush current, in-rush current can be regulated to an acceptable level. Notably, no additional impedances are required in circuit pathways that are subjected to startup in-rush current to limit in-rush current, thus avoiding loss of efficiency.

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Basingstoke, United Kingdom

Antony Christopher Routledge