International Business Machines Corporation

Antonius Paulus Engbersen

Ronald Pete Luijten

Jan Van Lunteren

Wolfgang Emil Denzel

Cyriel Johan Minkenberg

Francois Abel

Mitch Gusat

Ferdinand Gramsamer

Mark Verhappen

Yiyu L Chen

Andreas Guenther Herkersdorf

Martin L Schmatz

Mircea R Gusat

Gary Scott Delp

Alan Frederic Benner

Julian Satran

Gottfried Andreas Goldrian

Robert Birke

Peter L Buchmann

Thomas Basil Smith, Iii

David J Webb

Edi Shmueli

Hamid Ahmadi

Johannes G Beha

Michel Colmant

Marco Heddes

Sebastiano Spicuglia

Jason Juan Hernandez

Jose Duato

Charles Allen Murphy

Erich Port

Fran&ccedil;ois G Abel

Marinus J Van Weert

Cheng Wang

A computing system comprises one or more multicore processor(s) comprising a set of multiple processing units each operable at a variable frequency, and a main memory operable at a variable frequency. A feedback controller is configured to control the frequency of each processing unit of the set and the frequency of the main memory dependent on a measure representative of a current performance of an application running on one or more of the multiple processing units of the set.

Controlling power consumption

In some embodiments of this disclosure, a computer-implemented method includes accessing a set of two or more activity logs associated with two or more virtual machines, each activity log being associated with a corresponding virtual machine. A computational capacity is calculated, by a computer processor, for each of the virtual machines based at least in part on the activity logs. A rank is calculated for each of the virtual machines, where a first rank calculated for a first virtual machine is based, at least in part, on a monetary cost of the first virtual machine and the calculated computational capacity of the first virtual machine.

Calculating the rank of multiple virtual machines based on a negative correlation between the rank and each of the computational capacity and monetary investment

The present invention discloses a memory sharing mechanism based on priority elevation. In accordance with the present invention, there is provided an apparatus and method for transporting packets of data in a communication device, wherein each packet is assigned one of several priorities and received based on memory state information. The method comprises the steps of storing the received packets in a memory and modifying the assigned priority of any of the packets causing congestion within the memory.

Memory sharing mechanism based on priority elevation

A method and system for enabling management of a plurality of messages in a communication network is provided. The method includes measuring an in-load and an out-service corresponding to a plurality of switching-nodes in the communication network. The method further includes marking at least one message in a switching-node with an Explicit Congestion Notification (ECN) to form at least one Precise ECN (PECN)-message, if at least one predefined criterion corresponding to a switching-node evaluates to true. Each PECN-message is encoded with measurements of the in-load and the out-service corresponding to the switching-node. Thereafter, one or more management functions are performed to modify egress of the plurality of messages from a source-node. The source-node transmits the plurality of messages to a destination-node through the switching-node.

System and method for enabling management of a plurality of messages in a communication network

An apparatus for classifying a data packet includes an interface for receiving the data packet; a classification controller for parsing the data packet to identify a plurality of data items required for classifying the data packet; memory for storing a set of range identifiers for each data item in the data packet corresponding to a rule range defined in the rule sets; and a controller for performing a preliminary test of at least one of the data items to determine whether any of the data item's values match known frequently-occurring values for that data item.

Packet classification

Discloses a switching arrangement for packets of data, with several input ports and several output ports and which is determined for the transportation of incoming packets to one or more designated of the output ports and from there to a subsequent device. More particularly it relates to a switching arrangement and method wherein for each input port a set of output buffers is arranged, each set comprising an output buffer for each output port.

Switching arrangement and method with separated output buffers

A system and method for unifying access to a physical memory by operations using virtual addresses of the same virtual address space are provided. The operations may be generated by at least one central processing unit (CPU operations) and/or by at least one IO device (IO operations). The system may include a bus arranged to transfer data and virtual addresses of the same virtual address space from the central processing unit (CPU) and the IO device to a unified memory management unit (UMMU), a unified memory management unit (UMMU) arranged to translate the virtual addresses to physical addresses, and to protect the physical memory from illegal access attempts of the CPU operations and the IO operations. The system may further include a memory controller arranged to manage access to the physical memory. The access is done by using physical addresses.

Method and system for unifying memory access for CPU and IO operations

A method for automatically managing a virtual output queuing system in a switching fabric. The method includes detecting if a link is one of a non-operational-link and an operational-link. The link enables communication between a first-switching-unit and a second-switching-unit. If the link is the non-operational-link, the method further includes discarding at least one packet destined for the link. The discarding step further includes either dropping of the at least one packet or scheduling the at least one packet.

Method for automatically managing a virtual output queuing system

Methods and apparatus are provided for classifying data packets in a data processing device. In one aspect, packets are classified according to a plurality of sets of processing rules. Each rule defines a plurality of rule ranges, each rule range indicating a range of possible values of a corresponding data item in the packet for which the rule applies, and rule ranges defined in different rule sets correspond to a common set of data items. Independent item searches are performed for respective data items in the packet corresponding to rule ranges defined in the rule sets. The item search for a data item comprises selecting a range identifier corresponding to the value of the data item from a predetermined set of range identifiers for that data item. This set of range identifiers indicates, for all possible values of the data item, which of the rule ranges corresponding to the data item in the rule sets a value intersects. Next, respective final searches are performed for the rule sets based on range identifiers selected by the item searches. The final search for each rule set uses the selected range identifier for each data item corresponding to a rule range defined in that rule set, and predetermined rule data encoding the rule ranges for rules in that set, to identify at least one rule of any rules in the set which are applicable to the data packet. Thus packets can be classified according to multiple rule sets, but the initial item searches are performed only once, for all the rule sets.

Methods and apparatus are provided for classifying data packets in a data processing device according to a set of processing rules, wherein, for each of a predetermined group of data items in each packet, each rule defines a rule range indicating a range of possible values of the corresponding data item for which that rule applies. The method comprises for each data packet: (a) performing a preliminary test for at least one data item in said group, the preliminary test comprising testing the value of the data item in the packet for a match with any of a predetermined set of frequently-occurring values for that data item, each frequently-occurring value being associated with a predetermined indicator, and, if a match is obtained, selecting for the data item the indicator associated with the matching frequently-occurring value; (b) performing an item search for any data item in the group for which no match is obtained in a preliminary test, the item search for a said data item comprising selecting a range identifier corresponding to the value of the data item from a predetermined set of range identifiers for that data item, the set of range identifiers indicating, for all possible values of the data item, which of the rule ranges corresponding to the data item in the rule set a value intersects, wherein the indicator associated with a said frequently occurring value for a data item is the range identifier corresponding to that value of the data item; and (c) identifying, based on the selected range identifiers for all data items in the group, at least one rule of any rules applicable to the data packet.

The present invention discloses a scalable flow-control mechanism. In accordance with the present invention, there is provided a switching device for transporting packets of data, the packets being received at the switching device based on flow-control information, the device comprising a memory for storing the packets, a credit counter coupled to the memory for counting a credit number of packets departing from the memory, and a scheduler unit coupled to the credit counter for deriving the flow-control information in response to the credit number. Moreover, a switching apparatus and a method for generating flow-control information is disclosed.

Scalable link-level flow-control for a switching device

Methods and apparatus are provided for classifying data packets in data processing systems. A first packet classification method determines which of a plurality of predefined processing rules applies to a data packet, where each rule is associated with a range of possible data values in each of a plurality of dimensions (X,Y) corresponding to respective data items in the packet format. For each dimension (X,Y), it is determined which of a set of predefined basic ranges contains the corresponding data value (I, I) from the packet, where the basic ranges correspond to respective non-overlapping value ranges between successive rule range boundaries in the dimension. For the basic range so determined for each dimension, a corresponding basic range identifier is selected from a set of predefined basic range identifiers corresponding to respective basic ranges in that dimension. For each of at least two dimensions (X,Y), the basic range identifiers comprise respective p-bit strings generated independently for that dimension by a process of deriving a primitive range hierarchy based on the rule ranges in that dimension. The resulting basic range identifiers, one for each dimension, are then combined to produce a search key which is supplied to a ternary content-addressable memory (). In the memory (), the search key is compared with a set of ternary rule vectors, each associated with a particular rule and derived for that rule from the aforementioned hierarchies, to identify at least one rule which applies to the data packet. A second method classifies data packets according to the values in respective data packets of a single, predetermined data item (DA) in the data packet format, where a plurality of classification results are predefined for respective ranges of values of the data item (DA). Here the data item (DA) in the packet is first segmented. The resulting segments are then equated to different dimensions (X,Y) of a multidimensional packet classification problem and are processed in a similar manner to identify a classification result for the packet.

A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.

Load balancing system, apparatus and method

An integrated circuit (i.e., chip under test) includes a control and monitor interface that includes on-chip support for one or more network protocols that allow the chip to be directly coupled to a network. The control and monitor interface defines one or more operations that can be performed on the chip. In a system for testing chips under test, the control and monitor interface of all of the chips under test are coupled to a network, which is also coupled to a control and monitor mechanism. When a chip under test receives a message on the network from the control and monitor mechanism to execute an operation, it performs the requested operation, then reports the results. In this manner much of the intelligence regarding the test can be pushed on-chip, rather than having all of the testing intelligence residing in an external tester. This allows some standardization in tests that are performed from one chip under test to the next.

Integrated circuit with a VLSI chip control and monitor interface, and apparatus and method for performing operations on an integrated circuit using the same

Growing community of inventors

Feusisberg, Switzerland

Antonius Paulus Engbersen