International Business Machines Corporation

Antonius J Engbersen

Wolfgang Emil Denzel

Ronald Pete Luijten

Andreas Guenther Herkersdorf

Ernst H Rothauser

Marco Heddes

Gunnar Karlsson

A modular system for a buffer memory used for storing output queues (80a-k) of a packet switch is described. A series of memories (90) are each connected to both the input lines (10a-k) and the output lines (160a-k) of the switch. Each memory (90) is provided with a memory controller (100) connected to a latch (50) which is in turn connected to AND gates (60a-k). These AND gates (60a-k) ensure that packets are only stored in the memory (90) of the module in which the first latch (50) is set. When the memory (90) is full, the memory controller (100) resets this first latch (50) in the current module and sets the corresponding first latch (50) in the next module. The packets are then read into the memory (90) of the next module. A marker circuit (70) is used to insert in the output queues (80a-k) a marker to indicate that the next entries of the queue are to be found in the next module. On reading out the packets, this marker is detected by a detector (110a-k) which then resets a second latch (140a-k) in the module from which the packets are currently being read and sets a corresponding second latch (140a-k) in the next module. AND gates (150a-k) ensure that packets are only read out of those output buffer queues (80a-k) whose corresponding second latch (140a-k) is set. Each of the switch output lines (160a-k) can therefore only receive packets from one module. Different switch output lines (160a-k) will, however, receive packets from different modules.

Modular buffer memory with separately controllable logical output queues

The dynamic functional behavior of geographically distributed fast packet switching systems, including those which accommodate high-priority circuit switched traffic and low-priority packet switched traffic, are tested in real-time by sending test packets from one or more source nodes through the system to specific destinations that comprise a test packet analyzer. The test packets have the same structure as the data packets, but in their payload portion carry the entire information required to perform the testing. The nature of that test information depends on the characteristics of a set of predefined system errors the verification system is supposed to identify. For detecting errors, the test information would include an input address indicating the source of the test packet, a sequence number defining the order in which the packet should arrive at the destination, time bits relating to the packet length and/or to the expected packet transmission delay, and a cyclic redundancy code which covers the entire contents of the test packet, including its control portion. Each analyzer at a receiving station operates autonomously from the senders and processes all received traffic in real-time; this enables it to recognize all defined system errors, even those occurring with very low probability, at the packet level.

Method and apparatus for testing and evaluation of distributed networks

A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130, 230) and outputs it on adjacent output lines (140, 150, 240, 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270).

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Richterswil, Switzerland

Antonius J Engbersen