Nxp B.v.

Nxp Usa, Inc.

Antonius Hendrikus Jozef Kamphuis

Johannes Cobussen

Mustafa Acar

Jan Willem Bergman

Rajesh Mandamparambil

Amar Ashok Mavinkurve

Paul Mattheijssen

Guido Albermann

Philipp Franz Freidl

Michael B Vincent

Antonius Johannes Matheus De Graauw

Jeroen Johannes Maria Zaal

Jetse De Witte

Ernst Eiper

Marcellinus Johannes Maria Geurts

Chantal Claude Dijkstra

Johannes Henricus Johanna Janssen

Andrei-Alexandru Damian

Scott M Hayes

Franciscus Petrus Widdershoven

Dominicus Martinus Wilhelmus Leenaerts

Christian Zenz

Adrianus Buijsman

Jan Gulpen

Joep Stokkermans

Johannes Wilhelmus Dorotheus Bosch

Thomas Markus Kampschreur

Paul Southworth

Keith Richard Sarault

Wilhelmus Johannus Theodorus Derks

Leon Wetzels

Leendertjan Mekking

Sander Jacobus Geluk

Konstantinos Giannakidis

Erik Daniel Björk

One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.

On-chip shielded device

A semiconductor device may include an antenna array and a grounding assembly configured to at least partially electrically shield the antenna array. The grounding assembly may include a first grounding layer comprising a first plurality of openings and a second grounding layer comprising a second plurality of openings. The second grounding layer may at least partially occlude the first plurality of openings of the first grounding layer when viewed from above the antenna array.

Grounding assembly for a semiconductor device

An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.

Single die design for different polarizations

A semiconductor device comprising a substrate, a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array having a uniform pitch, and a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array having a uniform pitch. The second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch. Also provided is a method of manufacturing a multi-package module and a method of providing package-to-package grounding.

Semiconductor device having uniform multi-package antenna array and method of manufacture

Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Method and system for regulating plasma dicing rates

A Radio Frequency, 'RF', component and a method of making the same. The component includes a first electrically conductive signal member for conveying an RF signal and a second electrically conductive signal member for conveying an RF signal. The component also includes a barrier located between the first signal member and the second signal member electromagnetically to shield the first and second signal members from each other. The barrier includes a first row of electrically conductive shielding members spaced apart along a longitudinal axis of the first row, and a second row of electrically conductive shielding members spaced apart along a longitudinal axis of the second row. Each shielding member includes a polyhedron. The shielding members of the first row are offset with respect to the shielding members of the second row to prevent a direct line of sight between the first signal member and the second signal member.

RF component and method

A method of forming a self-aligned waveguide is provided. The method includes forming a first alignment feature on a packaged semiconductor device and a second alignment feature on a waveguide structure. A solder material is applied to the first alignment feature or the second alignment feature. The waveguide structure is placed onto the packaged semiconductor device such that the second alignment feature overlaps the first alignment feature. The solder material is reflowed to cause the waveguide structure to align with the packaged semiconductor device.

Semiconductor device with self-aligned waveguide and method therefor

A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

Technique for handling diced wafers of integrated circuits

A technique for handling an integrated circuit tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit tape assembly on a film frame carrier (FFC) frame, stretching the dicing tape while on the FFC frame, and securing the stretched dicing tape by engaging a spring ring with the dicing tape and FFC frame. Adjacent integrated circuits are thereby inhibited from colliding during shipment or storage for subsequent processing.

Aspects are directed to a waveguide structure that can couple to an integrated circuit package. The IC package includes a plurality of pillars to provide a path for carrying millimeter-wave signals, each of the pillars having a first end portion to connect to the IC package and a second end portion to connect to a waveguide antenna. Also, as may be optionally included, waveguide shields provide electro-magnetic isolation for the pillars and a micro-strip connector to provide connection between the second end portions (of the pillars) and to the waveguide antenna. Further included in the apparatus are a plurality of bond wires to connect the IC package and a lead frame, and to carry signals form circuitry of the IC package to the printed circuit board on which the package is mounted for transmission of radar signals via the waveguide antenna.

Apparatuses and methods for coupling a waveguide structure to an integrated circuit package

A mechanism is provided to reduce a distance of a waveguide antenna from transmit and receive circuitry in an integrated circuit device die. This distance reduction is performed by providing vertical access to radio frequency connections on a top surface of the IC device die. A cavity in the encapsulant of the package can be formed to provide access to the connections and plated to perform a shielding function. A continuous connection from the RF pads is used as a vertical interconnect. The region around the vertical interconnect can be filled with encapsulant potting material and back grinded to form a surface of the semiconductor device package. A waveguide antenna feed can be plated or printed on the vertical interconnect on the surface of the package.

Semiconductor device package comprising an encapsulated and conductively shielded semiconductor device die that provides an antenna feed to a waveguide

Embodiments are provided for a packaged semiconductor device including: a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; and a top cover including a soft-magnetic material positioned on the back side of the semiconductor die, wherein the top cover includes a recess formed in a first major surface of the top cover, the first major surface faces the back side of the semiconductor die, and the recess is positioned over the MRAM cell array.

Magnetic shielding structure for MRAM array

Optical control modules for integrated circuit device patterning and reticles and methods including the same. The methods include exposing, via a reticle, initial and subsequent reticle exposure fields on a surface of a semiconductor substrate. The initial and subsequent reticle exposure fields pattern corresponding array regions and margin regions on the semiconductor substrate. The initial and subsequent reticle exposure fields partially overlap such that an initial optical control module (OCM), which is patterned during exposure of the initial reticle exposure field, and a subsequent OCM, which is patterned during exposure of the subsequent reticle exposure field, both are positioned within a single control module die. The reticles include reticles that can be utilized during the methods or that can form the integrated circuit devices. The integrated circuit devices include integrated circuit devices formed utilizing the methods or the reticles.

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Lent, Netherlands

Antonius Hendrikus Jozef Kamphuis