Nxp USA, Inc.

Freescale Semiconductor,inc.

Antonio Mauricio Brochi

Frank Herman Behrens

Richard Soja

Felipe Ricardo Clayton

Marcelo Marinho

Patricia Elaine Domingues

Narcizo Sabbatini, Jr

An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.

Power profiling in an integrated circuit having a current sensing circuit

Systems and methods for protocol-tolerant communications in a Controller Area Network (CAN) are described. In some embodiments, a method may include receiving a frame at a network node; identifying, by the network node, a bit in a selected field of the frame; and determining, by the network node, that the frame follows a second format despite the bit indicating that the frame follows a first format. In other embodiments, a CAN controller includes message processing circuitry; and a memory coupled to the message processing circuitry, the memory having program instructions that configure the message processing circuit to: receive a frame; identify a bit in a selected field of the frame; and determine that the frame follows a Classical CAN format despite the bit indicating that the frame follows a flexible data-rate CAN (CAN FD) format.

Protocol-tolerant communications in controller area networks

A reconfigurable register device includes an arrangement of storage elements arranged sequentially in a chain structure. Each storage element stores a state of a binary signal. A combinatorial logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a binary synchronous counter. A bypass logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a serial shift register. A switching circuitry has a mode signal input terminal receiving a mode signal indicative of at least one of a counter mode and a shift register mode. The switching circuitry is configured to connect the arrangement of storage elements to the combinatory logic circuitry if the mode signal indicates the counter mode, and to connect the arrangement of storage elements to the bypass logic circuitry if the mode signal indicates the shift register mode.

Configurable serial and pulse width modulation interface

Systems and methods for multi-frame and frame streaming in a Controller Area Network (CAN) with Flexible Data-Rate (FD). In some embodiments, a method may include creating, by a device coupled to a CAN network configured to support a CAN Flexible Data-Rate (FD) protocol, a data frame comprising a field that indicates a multi-frame or streaming transmission, and transmitting the data frame in the multi-frame or streaming transmission. A CAN node may include message processing circuitry configured to receive a data frame comprising a Data Length Code (DLC) field configured to indicate multi-frame operation or streaming operation. The message processing circuitry may be further configured to receive another data frame in the absence of an arbitration process between the data frames.

Multi-frame and frame streaming in a controller area network (CAN) with flexible data-rate (FD)

A method for allocating memory that is associated with a CAN (controller area network) controller, comprises receiving a data frame comprising an identifier (ID) and data; dynamically allocating a message buffer (MB) within the memory for queuing the data frame; and generating a pointer that points to the MB, where the pointer is accessed via a static location in the memory. A corresponding host interface for the CAN controller can be implemented in IC circuitry, is configured to be coupled to a host CPU and a CAN bus interface, and includes a memory allocation unit for dynamic memory allocation and a memory access controller, coupled to the memory allocation unit and the memory, that is configured to control access to the memory to facilitate transmitting and receiving a multiplicity of data frames over a CAN bus.

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Campinas, Brazil

Antonio Mauricio Brochi