Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Antonio Magazzu'

Salvatore Vincenzo Capici

Giuseppe Gramegna

Bruno Ferrario

Alessandra Toscano

Carmelo Settepani

A low noise adaptive bias circuit is provided for a low noise bipolar junction input transistor having an emitter degeneration inductance, of an integrated high frequency functional circuit driven by the collector current of the input transistor. The bias circuit includes a shunt line connecting the base node of the input transistor to a first supply node of opposite sign of that of a second supply node to which is coupled, through the degeneration inductance, to the emitter of the input transistor. The shunt line includes a bias current generator dependent, in an inversely proportional manner, on the current gain of the input transistor, and a resistance dependent, in a directly proportional manner, on the current gain of the input transistor.

Precision low-noise current mode biasing scheme for BJT with inductive emitter degeneration

A synchronization circuit for electronic devices and components, being of the type which includes an internal synchronization signal generator and an input/output terminal whereat an external synchronization signal can be received. The synchronization circuit further includes a comparator for receiving both synchronization signals and having a control output for supplying a terminal with the signal corresponding to the master/slave mode of operation of the synchronization circuit. A method of generating and supplying a synchronization signal to a plurality of electronic devices being operated as slave devices to a synchronization circuit acting as the master device is also provided.

Clock circuit and corresponding method for generating and supplying a

A driver circuit is for turning on at least one power MOS transistor having a diode connected thereto. The driver circuit preferably includes a smart driver circuit portion for increasing a drive current to the power MOS transistor responsive to turning on of the diode. The smart driver circuit may include a comparator having one input connected to the diode and a second input connected to a threshold signal indicative of the turning on of the diode. The smart driver circuit may also comprise: a first current source for supplying a first drive current; a second current source for supplying a second drive current; and a switch for connecting the second current source to the power MOS transistor responsive to the comparator. The smart driver circuit may further include a turn off circuit for turning off the increased drive current a predetermined time after turning on same, such as before turning off the first current. In addition, the second current source may supply a second drive current at least one order of magnitude larger that the first drive current. Of course, the driver circuit may be implemented with bipolar and MOS transistors Buck, boost, and buck-boost regulators may be implemented.

Driver circuit for MOS transistor switches in switching regulators and

Switching and propagation delays in generating a PWM control signal by a circuit that generally includes an error amplifier, a sawtooth oscillator and a comparator for comparing the error signal with the sawtooth signal, is compensated by generating a second sawtooth signal synchronous with the master sawtooth signal but having a reduced discharge time and by applying the second synchronous sawtooth signal to the respective input of the PWM comparator.

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Messina, Italy

Antonio Magazzu'