Intel Corporation

Antonio González

Xavier Vera

Grigorios Magklis

Fernando Latorre

Jaume Abella

José González

Osman Unsal

Oguz Ergin

Pedro Marcuello

Pedro Chaparro Monferrer

Qiong Cai

Josep M Codina

Enric Gibert

Javier Carretero Casado

Hong Wang

Per H Hammarlund

Perry H Wang

John P Shen

Jared Warner Stark, Iv

Pedro Lopez

Jose Gonzalez

Gerolf F Hoflehner

Steve Shih-wei Liao

Tor M Aamodt

Carlos Madriles Gimeno

F Jesús Sánchez

José Alejandro Piñeiro

Pedro López

Carlos García Quinones

Jesús Sánchez

Pedro Chappero Monferrer

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Thread migration to improve power efficiency in a parallel processing environment

Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.

Replacement policy for hot code detection

Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.

Memory apparatuses with low supply voltages

A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Frequency and voltage scaling architecture

In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Detecting soft errors via selective re-execution

Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.

Protecting data storage structures from intermittent errors

In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.

Access of register files of other threads using synchronization

Techniques for achieving coherence between dynamically optimized code and original code are disclosed. In an embodiment, a search is performed for a first entry for a first page containing a first code region in a first data structure. The first code is used to determine whether a first indicator in the first entry is set to a first value. The first entry is added to the first data structure, in response to failing to find the first entry in the first data structure. A second search may be performed for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value. Other embodiments are also disclosed and claimed.

Achieving coherence between dynamically optimized code and original code

In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

Enabling speculative state information in a cache coherency protocol

The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating a remaining lifetime of the device based on the dynamic usage. Depending on the estimated remaining lifetime, the device may be controlled in a desired manner.

Dynamically estimating lifetime of a semiconductor device

In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.

Enhancing reliability of a many-core processor

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Growing community of inventors

Barcelona, Spain

Antonio González