Intel Corporation

Crown Cork & Seal Technologies Corporation

Obrist Closures Switzerland Gmbh

Antonio Gonzalez

Jose Gonzalez

Xavier Vera

Jaume Abella

Fernando Latorre

Grigorios Magklis

Pedro Lopez

Pedro Marcuello

Josep M Codina

Javier Carretero Casado

Pedro Chaparro Monferrer

Raul Martinez

Vivek K De

Ming Lei Zhang

Muhammad M Khellah

Christopher B Wilkerson

Ronny Ronen

Marc Lupon

Hong Wang

Ravishankar Iyer

Christopher Paul Ramsey

Polychronis Xekalakis

Qiong Cai

Per H Hammarlund

Perry H Wang

John P Shen

Donald K Newell

Srihari Makineni

Jared Warner Stark, Iv

Sylvia Maria Farrow

Jaideep Moses

Gerolf F Hoflehner

Ryan N Rakvic

Bernard Guglielmini

Carlos Madriles

Enric Gibert Codina

Jose-Alejandro Pineiro

Jesus Sanchez

Pedro Chaparro

Daniel Ortega

Kyriakos A Stavrou

Osman Unsal

Demos Pavlou

Georgios Tournavitis

Mirem Hyuseinova

Crispin Gomez Requena

Christos E Kotselidis

Carlos Garcia

Alejandro Martinez Vicente

Peter Rundberg

Alejandro Martinez Vincente

Steve Shih-wei Liao

Guillermo Savransky

Oguz Ergin

Tor M Aamodt

Enric Gibert

Ramesh G Illikkal

Carlos Madriles Gimeno

Alejandro Vicente Martinez

Fernando LaTorre

Joseph M Codina

Carlos García Quiñones

Eduardo Mingo Bonifacio

Felip Jornet Grino

Marti Torrents Lapuerta

Alejandro Martinez

Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.

Merging level cache and data cache units having indicator bits related to speculative execution

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Disabling cache portions during low voltage operations

A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region

Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.

Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Managed instruction cache prefetching

A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Frequency and voltage scaling architecture

Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution

According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.

Branch pruning in architectures with speculation support

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Speculative multi-threading for instruction prefetch and/or trace pre-build

Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.

Reducing aging effect on registers

A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

Multithreaded clustered microarchitecture with dynamic back-end assignment

Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer for later validation. A global register file holds the committed architecture state generated by a non-speculative thread. Each thread unit includes a local register file. A directory indicates, for each architectural register, which speculative thread(s) have generated a value for the architectural register. Other embodiments are also described and claimed.

Multi-version register file for multithreading processors with live-in precomputation

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Barcelona, Spain

Antonio Gonzalez