Stmicroelectronics S.r.l.

Alma Mater Studiorum-Universitá Di Bologna

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Paioli S.p.a.

Antonio Gnudi

Eleonora Franchi Scarselli

Roberto Antonio Canegallo

Marco Pasotti

Marcella Carissimi

Roberto Guerrieri

Mauro Scandiuzzo

Andrea Lico

Alessio Antolini

Giulio Ricotti

Luca Perilli

Alessia Maria Elgani

Biagio Giacalone

Dario Bruno

Federico Natali

Gianni Generali

Laura Paioli

Primo Ricciotti

Paolo Romele

Francesco Renzini

Matteo D'Addato

A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.

Threshold voltage generator circuit and corresponding receiver device

An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.

Signed and binary weighted computation for an in-memory computation system

A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

In-memory computation system with drift compensation circuit

An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.

Compensated analog computation for an in-memory computation system

In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.

Detection circuit, corresponding device and method

A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.

Method for verifying the alignment between integrated electronic devices

A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage. The reception calibration stage includes: a reception amplifier of a variable-gain type, having an input coupled to the reference capacitor, and a gain controller, having an input coupled to an output of the reception amplifier and an output coupled to control terminals of the reception and calibration amplifiers.

Electronic circuit for communicating through capacitive coupling

A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal.

A transistor threshold extraction circuit including at least two transistors of the same type each having a control terminal and having essentially a same threshold voltage, each of the two transistors also having first and second main conduction terminals, a current mirror circuit having at least two input-output terminals with the two terminals coupled respectively to the two transistors so as to supply bias currents, a voltage generator connected between the two control terminals, and a feedback path between the control terminals and one of the input-output terminals. An output of the extraction circuit is coupled to one of the control terminals.

Threshold extracting method and circuit using the same

The bicycle frame comprises a saddle tube, a steering head receiving a front fork rotatably therein, a frame top tube interconnecting top ends of the saddle tube and steering head, a front down tube interconnecting bottom ends of the saddle tube and steering head, and a rear fork assembly for supporting the rear wheel. The bottom ends of the saddle tube and front down tube are removably inserted and lockable in a crank axle block carrying the pedals. The front down tube and top tube have their front ends pivotally connected to the steering head and are provided with mutual locking means. A rear end of the top tube is connected to a sleeve positionable along the saddle tube.

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Bologna, Italy

Antonio Gnudi