Stmicroelectronics S.r.l.

Telefonaktiebolaget Lm Ericsson (publ)

Antonio Giordano

Nicola Errico

Luigi Sole

Orazio Pennisi

Leonardo Pedone

Luca Finazzi

Rossella Gaudiano

Giuseppe Fasolino

Giovanna Spadaccio

Roberto Giglio

Luca Marchesano

Marta Cantarini

Tiziana Bellavista

Arturo Orlandino

A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.

System basis chip having selectable power sequence configurations, corresponding processing system, device and method

In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the reference signal, a slave timing stage and a slave synchronization stage.

Timing system including a master device and at least a slave device synchronized with each other and related synchronization method

A circuit includes comparator circuitry to sense a current through a load and compare the intensity of the current with a comparison threshold which can be set to a first, lower threshold value and a second, higher threshold value. Logic circuitry receives from the comparator circuitry a comparison signal having a first value or a second value based on whether the intensity is lower or higher than the comparison threshold. The logic circuitry is configured to assert a first overcurrent event signal or a second overcurrent event signal based on the comparison signal having the first value or the second value and the comparison threshold set to the first or second threshold value.

Overcurrent detection circuit, corresponding system and method

A mechanism for maintaining the same communication identity number when intercepted calls are forwarded is embodied in various methods, devices and media-storing software.

Call forwarding detection in voice over packet interception

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Milan, Italy

Antonio Giordano