Bell Communications Research, Inc.

Rca Inc.

Antonio Fernandez

John D Robbins

E Scott Soper

Martin J Jaquez

Rashid Ansari

Hugo P Gaggioni

Hugo Pineiro Gaggioni

A system for combining a plurality of video signals and various forms of still imagery such as text or graphics into a single high resolution display is disclosed. The inventive system utilizes a multiport memory and a key based memory access system to flexibly compose a multiplicity of video signals and still images into a full color high definition television display comprising a plurality of overlapping windows.

Memory system for high definition television display

A system for combining a plurality of video signals and various forms of still imagery such as text or graphics into a single high resolution display is disclosed. The invention system utilizes a multiport memory and a key based memory access system to flexibly compose a multiplicity of video signals and still images into a full color high definition television display comprising a plurality of overlapping windows.

Raster assembly processor

A technique for the sub-band decomposition and reconstruction of video signals is disclosed. In an illustrative embodiment of the present invention, each field of a video signal is decomposed into sub-bands utilizing a polyphase filter bank unit including an infinite impulse response allpass filter with coefficients that are powers of two. To reconstruct the original image, an FIR is utilized which approximates an IIR allpass filter This eliminates the need for a full field memory in the reconstruction process.

HDTV Sub-band coding using IIR filter bank

A successive approximation analog-to-digital converter (ADC) which uses pipeline processing techniques is disclosed. Each stage of the ADC uses a switched capacitor both as a sample and hold element and as a voltage subtracter. An analog potential is developed at terminal one of the capacitor and then the potential applied to the other terminal is changed by switching in or switching out a source of reference potential. The resulting analog value at the first end of the capacitor is the difference between the input value and reference potential. This value is applied to the next ADC stage. The polarity of this analog difference value determines the value of the digital bit signal produced by the stage.

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Brooklyn, NY, United States of America

Antonio Fernandez