Sgs-Thomson Microelectronics S.r.l.

Antonio Chiriatti

Biagio Giacalone

Vincenzo Daniele

Marco Masini

Mirella Benedetti

The circuit comprises: a pair of programmable cells connected in series, one conducting, the other one open, with one free terminal connected to the ground and the opposite free terminal connected to a supply voltage; a threshold circuit having one input connected to the node between the two programmable cells, a switching threshold lower than the difference between the supply voltage and the threshold voltage of one of the programmable cells, and an output adapted to assume one of two logic levels depending on whether the tension on the input is higher or lower than the threshold; and a first transistor which is connected between the ground and the opposite end of the pair of programmable cells, is normally off and has a gate which can be driven to make it conduct.

Programmable static selection circuit for programmable devices

A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multfunctional blocks.

Programmable logic device having a plurality of programmable logic

A programmable logic and analogic integrated device comprises a programmable logic section capable of constituting by programming a state machine which beside producing outpout logic signals in function of input logic signals may drive a digital-analog converter (DAC), the analog signal generated by which is managed as well as other analog signals which may be respectively fed to a number of analog input pins of the integrated device by the said programmable state machine by means of a plurality of integrated analog switches which also permit the output of the analog signal generated by the DAC through a buffered analog output pin of the device. An integrated comparator (zero-crossing detector) provides a comparison between two distinct external analog signals or between an external analog signal and the analog signal generated by the DAC for producing an output logic signal which may be fed to an input of the state machine for implementing a certain interaction function. The device is useful for a wide range of applications in lieu of a microprocessor based system.

Growing community of inventors

Reggio Calabria, Italy

Antonio Chiriatti