Stmicroelectronics S.r.l.

Stmicroelectronics R&d Limited

Antonio Borneo

Danilo Pietro Pau

Fabrizio Simone Rovati

Diego Melpignano

David Siorpaes

Paolo Zambotti

Mark Owen Homewood

Andrea Pagni

Daniele Lavigna

Vittorio Zaccaria

Fabrizio Lucini

Lanfranco Salinari

A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.

Parallel processing method and system, for instance for supporting embedded cluster platforms, computer program product therefor

A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.

Method and system for video decoding by means of a graphic pipeline, computer program product therefor

Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.

Process for running programs on processors and corresponding processor system

A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes: a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; and a FIFO. The FIFO is connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the received data can be supplied from the FIFO to the stream register unit. The Processing system also includes a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Processing system streaming data handling system and stream register

The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system, assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set of two successive bundles. The instructions of the sequence may be executed by the various processors of the system in conditions of binary compatibility.

Process for running programs with selectable instruction length processors and corresponding processor system

A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.

Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product

A method of filtering noise from digital pictures includes selecting a first set of pixels including the union of a pixel of the current picture to be filtered and a second set of pixels temporally and spatially near the pixel. A certain number of extended sums of values assumed by as many pre-established weight functions of the intensity of a selected video component on the first set of pixels is also calculated. The second set of pixels may belong to the current picture or to a preceding picture. Several noise filters for digital pictures are also provided.

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Matera, Italy

Antonio Borneo