Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Antonio Barcella

Marco Giovanni Fontana

Paolo Rolandi

Luigi Pascucci

Massimo Montanaro

Giorgio Oddone

Paolo Caprara

Loris Vendrame

Carmelo Paolino

A transistor includes a substrate region ( ) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region ( ) of the first type (P&plus;) of conductivity inside the substrate region ( ) and adjacent to a first terminal (C) of the transistor, a well ( ) of second type (N) of conductivity placed inside the substrate region ( ), wherein the well ( ) of second type (N) of conductivity includes at least a second contact region ( ) of a second type of conductivity (N&plus;) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions ( ) of the first type of conductivity (P&plus;) adjacent to a plurality of regions of a third terminal (E , . . . , E ) of the transistor interposed each one ( ) and other ( ) by proper insulating shapes ( ).

Multi-emitter bipolar transistor for bandgap reference circuits

A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.

Timesharing internal bus, particularly for non-volatile memories

A reading method for non-volatile memory cells is which includes a first step in which a memory cell of the matrix is selected by the row decoder and by the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a defined value and a third step during which the selected cell is read with a sensing ratio depending on the reading voltage of said cell. Moreover a device for the reading of the cells is described, which comprises a modulation branch with at least one modulation transistor and a load generator associated with said modulation transistor in such a way to modulate analogous the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.

Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method

The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

Method and device for reading a non-erasable memory cell

A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.

Method and circuit for trimming the internal timing conditions of a

In a first operation mode the level shifter transmits as output a logic input signal and in a second operation mode it shifts the high logic level of the input signal from a low to a high voltage. The level shifter comprises a CMOS switch and a pull-up transistor; the CMOS switch comprises an NMOS transistor and a PMOS transistor which are connected in parallel between the input and the output of the shifter and have respective control terminals connected to a first supply line at low voltage and, respectively, to a control line connected to ground in the first operation mode and to the high voltage in the second operation mode; the pull-up transistor is connected between the output of the shifter and a second supply line switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line.

Voltage level shifter device, particulary for a nonvolatile memory

The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

Hierarchic memory device having auxiliary lines connected to word lines

A non-volatile memory device having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus that runs from one end of the memory device to the other, one or more source structures that exist externally and internally to the memory device, and a timer means. The timer means is adapted to time-control the independent and exclusive access of the external and internal source structures, within a same memory cycle, to the internal bus for the transmission of data, controls, and functions, from one end of the memory to the other over the internal bus.

Non-volatile memory device having optimized management of data

A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.

Zero consumption power-on-reset

A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.

Data input/output managing device, particularly for a non-volatile memory

A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, where the memory is divided into at least two memory half-matrices that are arranged on different half-planes. The circuit includes, for each one of the at least two memory half-matrices, a reference unit for each one of the at least two memory half-matrices and an associated unit for reproducing the propagation of the signals along the reference unit. The reference unit and the associated propagation reproduction unit have a structure that is identical to each generic word line of the memory device. The reference and propagation reproduction units of one of the at least two memory half-matrices are activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit conditions for starting correct and certain reading of the selected memory cell.

Reference word line and data propagation reproduction circuit for

The differential input stage of a sense amplifier is provided with a positive feedback for introducing a predefinable hysteresis that will prevent spurious transitions of the output of the sense amplifier, enhancing noise immunity. The positive feedback is realized by employing an inverting amplifying stage, which will introduce an hysteresis on one of the two switching phases. The thresholds of the sense amplifier may be made symmetric by modifying the area ratio of the load transistors.

Sense amplifier with hysteresis

A latch circuit that is intentionally unbalanced, so that a first output reaches ground voltage and a second output reaches a supply voltage. The latch circuit may be used with a fully static low-consumption fuse circuit which reverses the first and second outputs of the latch circuit when the fuse is in an unprogrammed state, but does not change the outputs of the latch circuit in the programmed state. In particular, the latch circuit has a first transistor of a first polarity series connected at a first output node with a second transistor of a second polarity between a supply voltage and a ground voltage. A third transistor of the first polarity is series connected at a second output node with a fourth transistor of the second polarity between the supply voltage and the ground voltage. The gate terminals of the first and second transistors are connected to the second output, while the gate terminals of the third and fourth transistors are connected to the first output. The first and third transistors have thresholds which are mutually different, and the second and fourth transistors have thresholds which are mutually different, so that the first output reaches ground voltage and the second output reaches the supply voltage. This circuit can be combined with a fuse circuit, such as a dual gate transistor.

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Trescore Balneario, Italy

Antonio Barcella