Ati International Srl

Ati Technologies Inc.

Ati Technologies Ulc

Advanced Micro Devices Corporation

Antonio Asaro

Indra Laksono

Milivoje M Aleksic

Gordon Caruk

Andrew Evan Gruber

Carl K Mizuyabu

Brian Hiyin Lee

Raymond M Li

Danny H M Cheng

John Kalamatianos

Maurice B Steinman

Jonathan Mercer Owen

Guhan Krishnan

Ralf Flemming

Joerg Winkler

Thomas Kunjan

James Doyle

Don Cherepacha

David A Strasser

Allen J Porter

Paul Chow

Gordon Fraser Grigor

Kuldip Sahdra

Jason Chan

Steven Charles Dilliplane

Biljana D Simsic

Bo Liu

Nader Akhlaghi-Tavasoli

Lee Brian

Jason Ck Chan

Thomas R Kunjan

A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Hierarchical memory arbitration technique for disparate sources

A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

A configurable register method and structure included configuration logic to form a register value. A data bridge system, for connecting an interface of a computer system to a plurality of application-specific integrated circuits (ASIC), has a data bridge operatively coupled between the computer interface and the plurality of ASICs that employs the configurable registers. The data bridge has a read only memory for storing at least the initial values and mask values for each ASIC of the plurality of ASICs. The data bridge upon initialization forms base address registers and other configuration data that are queried by the computer system. When the ASICs are graphic processors, the initial values and the mask values stored in the read only memory define the base address registers in the data bridge as a function of the configuration requirements of the graphic processors. The base address registers are thus programmable as a function of the initial values and mask values in the read only memory. The read only memory is coupled to the data bridge.

Method and apparatus for a data bridge in a computer system

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

System of accessing data in a graphics system and method thereof

In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Apparatus and method for transmitting data

Method of configuring, controlling, and accessing a bridge and apparatus therefor

A method and apparatus for decompressing compressed data, which includes video data that has been compressed in accordance with the MPEG 2 standard, wherein the processing begins by retrieving components from a non-local memory at a rate that is independent of the rate in which the components were written into the non-local memory. The components include motion vectors and run/level data. As the components are retrieved from memory, the run/level data is used to produce representations of the uncompressed data. As the representations of the uncompressed data are generated, they are processed based on the motion vector data to recapture the uncompressed data. The uncompressed data is then stored in a frame buffer for subsequent display.

Method and apparatus for decompressing compressed data

In a specific embodiment, a system for providing video includes a system bus, which in one embodiment is an Advanced Graphics Port (AGP) busy. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Method and apparatus for routing data to multiple graphics devices

Multiple device bridge apparatus and method thereof

A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.

System and method for accessing video data using a translation client

Apparatus for providing data to a plurality of graphics processors and method thereof

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

Video controller for accessing data in a system and method thereof

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH and CH access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.

Graphics display list handler and method

A method and apparatus for improved concurrency within a video graphics process by generating culling information from geometry information. The geometry information corresponds to an image to be rendered, and the culling information indicates the triangles of the objects of the image that are in a front-facing or back-facing position. Having generated the culling information, set-up information is generated therefrom. The set-up information provides rendering data for the triangles of the object of the image being rendered. Next, pixel data is generated for a triangle based on the set-up information. To improve the concurrency, the queuing and the retrieval of the culling information and the set-up information from non-local memory are controlled such that the generating of the culling information, the set-up information, and the pixel data is done with improved concurrency.

Method and apparatus for improved concurrent video graphic processing

Growing community of inventors

Scarborough, Canada

Antonio Asaro