Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Sgs Microelettronica Spa

Antonio Andreini

Claudio Contiero

Paola Galbiati

Pietro Erratico

Enrico M Ravanelli

Pietro Consiglio

Giorgio Chiozzi

Riccardo Depetro

Alessandra Merlini

Lorenzo Cerati

Paola Galbiata

A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.

Semiconductor electronic device and method of manufacturing thereof

The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

VDMOS transistor protected against over-voltages between source and gate

N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.

Thin epitaxy resurf integrated circuit containing high voltage p-channel

Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.

Device for limiting the working voltage for mechanical switches in

Device for limiting the working voltage mechanical switches in telephony

This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

Method for manufacturing semiconductor integrated circuits including

An improved fabrication process for vertical DMOS cells contemplates the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, also allowing the forming the source region. Opening of the relative contact is also effected by a self alignment technique, further simplifying the process.

Self-aligned process for fabricating small DMOS cells

This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N.sup.+ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.

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Usmate Velate, Italy

Antonio Andreini