Micron Technology Incorporated

Stmicroelectronics S.r.l.

Other

Stmicroelectronics International N.v.

Lodestar Licensing Group LLC

Stmicroelectronics (rousset) Sas

Antonino Mondello

Alberto Troia

Francesco Tomaiuolo

Michelangelo Pisasale

Tommaso Zerilli

Michele Alessandro Carrano

Carmelo Condemi

Fabio Indelicato

Federico Tiziani

Riccardo Condorelli

Marco Ruta

Salvatore Giove

Maria Luisa Gambina

Pierluca Guarino

Carmela Maria Calafato

Giovanni Nunzio Maria Avenia

Zoltan Szubbocsev

Alessandro Inglese

Lance W Dover

Daniele Mangano

Mauro Luigi Sali

Michel Cuenca

Michele La Placa

Salvatore Pisasale

Francesco Mastroianni

Luc Garcia

Massimiliano Mollichelli

Pasquale Butta'

Stefano Catalano

Alessandro Tumminia

Luigi Buono

Martino Angelica

Cyril Pascal

Fabien Laplace

Salvatore Fava

Elena Cussotto

Vijay Kumar Malhi

A circuit implemented as a System-on-Chip (SOC) circuit comprising a microcontroller configured to drive one or more hard macros via a respective communication interface and a shielded bus. The microcontroller configured to transmit over the shielded bus random numbers to the hard macro. The microcontroller and the hard macro configured to use these random numbers as cryptographic shared secret for authentication. The microcontroller configured to drive via the communication interface the hard macros authenticated via the random numbers.

Circuit with hard macro protection and corresponding method

An electronic device includes at least two electronic components. A reset circuit includes: a parity control circuit; at least two first flip-flops, wherein each first flip-flop has an output coupled to at least one of the at least two electronic components; and at least two second flip-flops, wherein each second flip-flop has at least one output coupled to an input of the parity control circuit.

Reset circuit

A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.

System on chip including a PVT sensor and corresponding PVT sensing method

The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Memory component for a system-on-chip device

Apparatuses, methods, and systems for verifying a vehicular identity are described. An embodiment includes a processing resource, memory, and a vehicular communication component configured to verify an identity of the particular vehicle using a public key, wherein the public key is received in response to a departure of the particular vehicle, and request, in response to verifying the identity of the particular vehicle, data corresponding to information associated with the departure of the particular vehicle.

Verifying vehicular identity

An apparatus can include a processor and a vehicular communication component. The vehicular communication component can be configured to generate a vehicular private key and a vehicular public key, provide the vehicular public key to a plurality of external communication components wherein each respective one of the plurality of external communication components is positioned on a different transportation assistance entity, provide data to at least one of the plurality of external communication components, receive, in response to providing the data, additional data from the at least one of the plurality of external communication components, wherein the additional data is encrypted using the vehicular public key, and decrypt the additional data using the vehicular private key.

Secure vehicular communication

An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Artificial neural network integrity verification

A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.

Integrated electronic system with an improved power-on reset circuit and method for controlling the integrated electronic system

A method includes receiving, by a computing device, a message from a host device. In response to receiving the message, the computing device generates an identifier, a certificate, and a key. The identifier is associated with an identity of the computing device, and the certificate is generated using the message. The computing device sends the identifier, the certificate, and the key to the host device. The host device verifies the identity of the computing device using the identifier, the certificate, and the key.

Verification of identity using a secret key

A method includes: generating, based on a hash function using at least one input including first data, a first digest; storing the first data in a memory; reading the first data from the memory; generating, based on the read data, a second digest; comparing the first digest and the second digest; and determining, based on comparing the first digest and the second digest, whether the read data is corrupted.

Determining validity of data read from memory by a controller

An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

Memory device with serial and parallel testing structure for sensing amplifiers

The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Flash memory architecture implementing interconnection redundancy

According to one aspect, a system-on-a-chip is proposed which includes a memory storage, a computation circuit, a comparison circuit, and a validation circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute several modified software modules from the external software module and compute check values by iteration until obtaining a final check value. Each check value is computed at least from a given modified software module and a check value previously computed, starting with a predefined initial check value. The comparison circuit is configured to compare the final check value to an expected value stored in the system-on-a-chip. The validation circuit is configured to validate the external software module when the final check value is equal to the expected value.

Method for validating an external software module for its use by a system-on-a-chip

Disclosed are techniques for managing a platoon of autonomous vehicles. In one embodiment, a method is disclosed comprising establishing a network connection between a plurality of autonomous vehicles, the plurality of autonomous vehicles operating as a platoon; receiving a request from a first autonomous vehicle to deviate from the platoon, the request comprising a digitally signed message from the first autonomous vehicle; assigning the first autonomous vehicle as a second master autonomous vehicle; permanently recording the assignment in a blockchain data structure; instantiating a new platoon path using the first autonomous vehicle as a head of the new platoon path; and disconnecting one or more autonomous vehicles associated with the new platoon path upon determining that the new platoon path is stable, the disconnecting causing the second master autonomous vehicle to manage the one or more autonomous vehicles using a second blockchain stored on the second master autonomous vehicle.

Cryptography-based platooning mechanism for autonomous vehicle fleet management

The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises:

Growing community of inventors

Messina, Italy

Antonino Mondello