L-3 Communications Integrated Systems L.p.

Antone Lee Kusmanoff

Deepak Prasanna

Matthew Pascal DeLaquil

Gerald Lothair Fudge

Scott Michael Burkart

Jerry William Yancey

Joshua David Anderson

Ross E Bland

A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.

System for convergence evaluation for stationary method iterative linear solvers

A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.

Reconfigurable networked processing elements partial differential equations system

A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.

System for conjugate gradient linear iterative solvers

RF sampling receivers are disclosed that employ multiple sampling clocks to produce multiple projections. In operation, a Nyquist folded receiver (NYFR) may be implemented that utilizes at least one modulated sampling clock in combination with one or more other modulated or non-modulated sampling clocks to identify received signals. In such an embodiment, one or more clock modulations may be used to induce frequency modulations that are Nyquist zone dependent, and multiple Nyquist zones may be aliased together while still allowing for signals from different Nyquist zones to be separated and identified.

Multiple projection sampling for RF sampling receivers

Problem solution speed may be increased by dynamically changing processing device computational hardware configuration in concert with respective mathematical phases of an algorithm to match accuracy demands at various phases of computation. Smaller but faster hardware structures may be increased in size using real-time partial or full reconfiguration of a processing device to apply the smallest and fastest possible computational structure for the needed accuracy during each of multiple computational phases.

Multi-phased computational reconfiguration

A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.

Tiled architecture for stationary-method iterative linear solvers

Systems and methods for interference cancellation in which a first signal having a first frequency may be cancelled with a second frequency having a second and different (e.g., lower) frequency by employing sampling to cancel the first signal with the separate signal at the sample instances.

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Greenville, TX, United States of America

Antone Lee Kusmanoff