Tokyo Electron Limited

Micron Technology Incorporated

Nan Ya Technology Corporation

Anton J deVillers

Jeffrey Smith

Lars W Liebmann

Kandabara N Tapily

Kaveri Jain

Daniel J Fulford

Scott L Light

H Jim Fulford

Daniel Chanemougame

Lijing Gou

Michael D Hyatt

Mark I Gardner

Scott E Sills

Jianming Zhou

Jodi Grzeskowiak

Zishu Zhang

Dan B Millward

Yuan He

Subhadeep Kal

William R Brown

Anthony R Schepis

Ronald W Nasman

Adam L Olson

Erik R Byers

Ho Seop Eom

Gurtej S Sandhu

Hoyoung Kang

James Grootegoed

Gerrit J Leusink

Nihar Mohanty

Vishal Sipani

Lior Huli

Ranjan Khurana

Norman A Jacobson, Jr

Joshua Hooge

Xue Chen

Michael Carcasi

Shane J Trapp

Rodney Lee Robison

Corey Lemley

David Travis

Xue (Gloria) Chen

Kevin J Torek

Kevin R Shea

Akiteru Ko

David A Kewley

Andrew W Metz

Benjamen M Rathsack

Farrell Martin Good

Mirko Vukovic

Carlos A Fonseca

Michael Murphy

Robert C Carr

Prasanna Srinivasan

Hiroaki Niimi

Robert Daniel Clark

Kaushik Arun Kumar

Mark W Kiehlbauch

Hongbin Zhu

David L O'Meara

Anthony Dip

Alex J Schrinsky

Kai-Hung Yu

Richard Farrell

Eric Chih-Fang Liu

Teruhiko Kodama

Paul T Gutwin

Toshiharu Wada

Nathan Ip

Paul Gutwin

Joel Estrella

David C Conklin

David Hetzer

Robert Brandt

Brandon Byrns

Sanjana Das

Hiroki Niimi

Norman Jacobson

James M Buntin

Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.

Replacement buried power rail in backside power delivery

Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

Self-aligned method for vertical recess for 3D device integration

A patterning method includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist, deposited by spin-on deposition, over a second layer of a dry photoresist, deposited by vapor deposition. The multilayer photoresist stack is exposed to a first pattern of actinic radiation including relative, spatially-varying doses of actinic radiation and including high-dose regions, mid-dose regions and low-dose regions. The multilayer photoresist stack and the first pattern of actinic radiation are configured such that after the exposing the multilayer photoresist stack to the first pattern of actinic radiation, in the high-dose regions, developability of both the first layer and the second layer is changed; in the mid-dose regions, developability of the first layer is changed while developability of the second layer is unchanged; in the low-dose regions, developability of both the first layer and the second layer is unchanged.

Wet-dry bilayer resist dual tone exposure

A method of microfabrication is provided. A substrate having a working surface and having a backside surface opposite to the working surface is received. The substrate has an initial wafer bow resulting from one or more micro fabrication processing steps executed on the working surface of the substrate. The initial wafer bow of the substrate is measured and the initial wafer bow is used to generate an initial wafer bow value that identifies a degree of first order wafer bowing of the substrate. A correction film recipe based on the initial wafer bow value is identified. The correction film recipe specifies parameters of a correction film to be deposited on the backside surface of the substrate to change wafer bow of the substrate from the initial wafer bow to a modified wafer bow. The correction film on the backside surface of the substrate according to the correction film recipe is deposited. The correction film physically modifies internal stresses on the substrate and causes the substrate to have a modified bow with the predetermined wafer bow value.

Backside deposition tuning of stress to control wafer bow in semiconductor processing

A method of patterning a substrate includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist deposited by spin-on deposition, and a second layer of a dry photoresist deposited by vapor deposition. The first layer is positioned over the second layer. A first relief pattern is formed in the first layer by exposure to a first pattern of actinic radiation of a first wavelength and development of developable portions of the first layer using a first development process. The first relief pattern uncovers portions of the second layer. A multi-color layer of the first relief pattern is formed. The multi-color layer includes the wet photoresist and a third material that is different from the wet photoresist and the dry photoresist. A selective patterning process is executed for uncovered portions of one or two of the wet photoresist, the dry photoresist and the third material.

Selective patterning with wet-dry bilayer resist

A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

Method of patterning a substrate using a sidewall spacer etch mask

Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.

Power delivery network for CFET with buried power rails

A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks

A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.

Method of manufacturing a semiconductor apparatus having stacked devices

Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

Precision multi-axis photolithography alignment correction using stressor film

The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.

Method for tuning stress transitions of films on a substrate

A method of processing a wafer is provided. The method includes providing a reference pattern for patterning a wafer. The reference pattern is independent of a working surface of the wafer. A placement of a first pattern on the working surface of the wafer is determined by identifying the reference pattern to align the first pattern. The first pattern is formed on the working surface of the wafer based on the placement.

Method for producing overlay results with absolute reference for semiconductor manufacturing

In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory

Light can be used to monitor coating a liquid on a substrate. By directing the light to a spot on the substrate, when the liquid passes through the spot, some light will be reflected, while some light will be scattered. Monitoring this behavior can indicate whether a substrate has been successfully coated with the liquid, as well as identifying defects. Further, coating times can be monitored to make process adjustments.

System and method for liquid dispense and coverage control

A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking

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Clifton Park, NY, United States of America

Anton J deVillers