Advanced Micro Devices Corporation

Globalfoundries Inc.

Digital Equipment Corporation

Anton Chernoff

Mauricio Breternitz, Jr

Keith Lowery

Patryk Kaminski

Mark Douglas Hummel

Benjamin Charles Serebrin

David E Mayhew

Michael J Osborn

Venkata Krishnan

David A Kaplan

John S Yates, Jr

Joseph Lee Greathouse

Dz-Ching Ju

Steven Tony Tye

Michael John Bedy

Mark Herdeg

Bengamin Serebrin

The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes with the selected boot-time configuration to modify at least one boot-time parameter of the at least one node.

System and method for configuring boot-time parameters of nodes of a cloud computing system

A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.

User-level hardware branch records

The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes determining, based on a shared execution of a workload by a cluster of nodes of the computing system, that at least one node of the cluster of nodes operated at less than a threshold operating capacity during the shared execution of the workload. The method further includes selecting a modified hardware configuration of the cluster of nodes based on the determining such that the cluster of nodes with the modified hardware configuration has at least one of a reduced computing capacity and a reduced storage capacity.

System and method for modifying a hardware configuration of a cloud computing system

The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.

System and method for configuring a cloud computing system with a synthetic test workload

Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.

Systems and methods for sharing devices in a virtualization environment

In a processing system comprising a plurality of processing nodes coupled via a switching fabric, a method includes implementing a flow control property for a data flow in the switching fabric based on an addressing property of an address of a virtual network interface controller associated with the data flow. A switching fabric includes a plurality of ports, each port coupleable to a corresponding processing node, and switching logic coupled to the plurality of ports. The switching fabric further includes flow control logic to implement a flow control property for a data flow in the switching logic based on an addressing property of an address of a virtual network interface controller associated with the data flow.

Processing system using virtual network interface controller addressing as flow control metadata

The present disclosure relates to a method, system, and apparatus for configuring a computing system, such as a cloud computing system. A method includes, based on user selections received via a user interface, configuring a cluster of nodes by selecting the cluster of nodes from a plurality of available nodes, selecting a workload container module from a plurality of available workload container modules for operation on each node of the selected cluster of nodes, and selecting a workload for execution with the workload container on the cluster of nodes. Each node of the cluster of nodes includes at least one processing device and memory, and the cluster of nodes is operative to share processing of a workload.

System and method for configuring cloud computing systems

Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.

Systems and methods for input/output virtualization

A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line.

Programmable atomic memory using stored atomic procedures

A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit.

Automatic load balancing for heterogeneous cores

A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code.

Lightweight service based dynamic binary rewriter framework

A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.

Automatic kernel migration for heterogeneous cores

In one embodiment, a processor comprises a redirect unit configured to detect a match of an instruction pointer (IP) in an IP redirect table, the IP corresponding to a guest instruction that the processor has intercepted, wherein the guest is executed under control of a virtual machine monitor (VMM), and wherein the redirect unit is configured to redirect instruction fetching by the processor to a routine identified in the IP redirect table instead of exiting to the VMM in response to the intercept of the guest instruction.

Redirection table and predictor for fetching instruction routines in a virtual machine guest

A processor having one or more processor cores includes execution logic that may execute instructions including one or more processes. Each process may include one or more execution threads. The processor also includes a profiling mechanism that includes monitor logic and a monitor process. The monitor logic may monitor the one or more processes and provide access to performance data associated with the one or more processes without interrupting a flow of control of the one or more processes being monitored. The monitor process may gather the performance data. In addition, the monitor process may include program instructions executable by the one more processor cores while operating in user mode.

Mechanism for profiling program software running on a processor

A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process. The non-native image is executed in two different enviroments with first portion executed as an interpreted image and remaining portions as a translated image. The run-time system includes an interpreter which is capable of handling condition codes corresponding to the non-native architecute.

Growing community of inventors

Harvard, MA, United States of America

Anton Chernoff