Seagate Technology Incorporated

Cypress Semiconductor Corporation

Seagate Technologies, Inc.

Other

Seagate Technolagy LLC

Antoine Khoueir

Ryan James Goss

Ara Patapoutian

Haiwen Xi

Jon David Trantham

Darshana H Mehta

Kevin Arthur Gomez

David Scott Ebsen

Mark A Gaertner

Song Sheng Xue

Michael Xuefei Tang

Youngpil Kim

Rodney Virgil Bowman

Yongchul Ahn

Hongyue Liu

Young Pil Kim

Mehmet Emin Aklik

Frank R Dropps

Brian Lee

Dadi Setiadi

Kurt W Getreuer

Maroun Khoury

Nicholas Odin Lien

Peter Nicholas Manos

Insik Jin

Paul E Anderson

Shuiyuan Huang

Ivan Petrov Ivanov

Christopher Joseph Curl

Dimitar Velikov Dimitrov

Wei Tian

Harry Hongyue Liu

Chulmin Jung

Stacey Secatch

Michael Joseph Steiner

Hyung-Kyu Lee

Pat J Ryan

Jinyoung Kim

Hsing-Kuen Liou

Paramasiyan Kamatchi Subramanian

Namoh Hwang

H Jim Fulford

Yong Lu

Patrick Joseph Ryan

Olle Gunnar Heinonen

John D Stricklin

Zheng Wang

Andrey V Zagrebelny

Christina L Hutchinson

Scott Younger

Wei Wang

Shuiyan Huang

Subhash Srinivas Pidaparthi

Shuiyuan Haung

Lili Jia

Colin Hill

Varun Voddi

Method and apparatus for managing data in a cloud computing environment. In accordance with some embodiments, data updates are received to a multi-tier memory structure across a cloud network and stored as working data in an upper rewritable non-volatile memory tier of the memory structure. The working data are periodically logged to a lower non-volatile memory tier in the memory structure while a current version of the working data remain in the upper memory tier. The upper and lower memory tiers each are formed of rewritable memory cells having different constructions and storage attributes.

Data update management in a cloud computing environment

Weak erase detection and mitigation techniques are provided that detect permanent failures in solid-state storage devices. One exemplary method comprises obtaining an erase fail bits metric for a solid-state storage device; and detecting a permanent failure in at least a portion of the solid-state storage device causing weak erase failure mode by comparing the erase fail bit metric to a predefined fail bits threshold. In at least one embodiment, the method also comprises mitigating for the permanent failure causing the weak erase failure mode for one or more cells of the solid-state storage device. The mitigating for the permanent failure comprises, for example, changing a status of the one or more cells to a defective state and/or a retired state. The detection of the permanent failure causing the weak erase failure mode comprises, for example, detecting the weak erase failure mode without an erase failure.

Detection and mitigation for solid-state storage device read failures due to weak erase

Technologies are described herein for or extending the lifespan of a solid-state drive by using worn-out MLC flash blocks in SLC mode to extend their useful life. Upon identifying a first storage location in the storage media of an SSD as a candidate for defecting, the first storage location is switched from a first programming mode to a second programming mode, where the second programming mode results in a lower storage density of storage locations than the first programming mode. In conjunction with switching the first storage location to the first programming mode, a second storage location in the storage media is switched from the second programming mode to the first programming mode to ensure that the total capacity of the storage media remains at or above the rated capacity.

Extending the life of a solid state drive by using MLC flash blocks in SLC mode

Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

Mitigation of solid state memory read failures with a testing procedure

An apparatus comprises a mass storage unit and a plurality of circuit modules including a machine learning module, a programmable state machine module, and input/output interfaces. Switching circuitry is configured to selectively couple the circuit modules. Configuration circuitry is configured to access configuration data from the mass storage unit and to operate the switching circuitry to connect the circuit modules according to the configuration data.

Storage device with configurable neural networks

Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory region, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

Mitigation of solid state memory read failures

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

Random selection of code words for read voltage calibration

Mitigation of solid state memory read failures with peer based thresholds

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.

Master set of read voltages for a non-volatile memory (NVM) to mitigate cross-temperature effects

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.

Preemptive mitigation of cross-temperature effects in a non-volatile memory (NVM)

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.

Adjusting code rates to mitigate cross-temperature effects in a non-volatile memory (NVM)

Systems and methods presented herein provide for failure detection and data recovery in a storage system. In one embodiment, a method operable in a storage system comprises locating failures in data blocks in storage area of a storage device, categorizing the failures into block groups, each block group comprising one or more data blocks having failures, and halting input/output (I/O) operations to data blocks in a first of the block groups due to the failures of the first block group. The method also includes detecting additional failures in one or more data blocks of other block groups remaining in the storage area, and determining when to fail the storage area of the storage device based on the detected failures.

Failure detection and data recovery in a storage system

Method and apparatus for decoding error correction code (ECC) code words. Reference voltages are used to extract a selected code word from a communication channel. The selected code word is processed by an ECC decoder, and an initial syndrome weight is determined indicative of unresolved parity errors. A coarse search operates to concurrently adjust, over a first succession of iterations, each of the reference voltages. A subsequent fine search operates, over a second succession of iterations, to individually adjust the reference voltages. Decoding and syndrome weight determination continues over each iteration until a minimum syndrome weight is obtained, after which a user data content of the code word is decoded. The coarse search may transition the decoder from a saturated operational region to a linear operational region. The decoder may be a low density parity check (LDPC) decoder.

Fast error recovery with error correction code (ECC) syndrome weight assist

A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server. Based on cooperation between the user device and the network server, a boundary between the first portion and the second portion of the deep learning network is dynamically modified based on a change in a performance indicator that could affect the processing task.

Dynamically modifying a boundary of a deep learning network

Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.

Open block stability scanning

Growing community of inventors

Apple Valley, MN, United States of America

Antoine Khoueir