Koninklijke Philips Corporation N.V.

Antoine Farid Dagher

Farrell Lynn Ostler

George Samuel Fleming

A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions. Because cryptographic processes are characterized by operations on wide data items, particular emphasis is placed on the efficient processing of multi-word operations, including the use of constants having the same width as an instruction word. A simplified arithmetic unit is provided that efficiently supports the functions typically required for cryptographic operations with minimal overhead. A microcode-mapped instruction set is utilized in a preferred embodiment to facilitate multiple parallel operations in each instruction cycle and to provide direct processing control with minimal overhead.

Simple algorithmic cryptography engine

A processor architecture supports the decoupling of parameters typically associated with branch/jump instructions. Jump instructions are provided that do not contain an explicit destination address and other jump instructions are provided that do not contain an explicit test condition. The processing system provides a &ldquo;default&rdquo; value to any control element in the processor that is not expressly controlled by a particular instruction. In the case of a branch or call instruction, the default destination-address provided to effect the branch or call is the destination-address provided by a prior instruction. Subsequent or alternative branch or call instructions branch to this same address until the default address is set to a different address. In like manner, in most cases, the default condition that is used to determine the result of a conditional test, such as a conditional branch, call, or return instruction, is the last condition specified in a prior instruction.

Branch instructions with decoupled condition and address

A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a &ldquo;circular increment&rdquo; or &ldquo;circular decrement&rdquo; instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these &ldquo;bounds&rdquo; flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed.

Growing community of inventors

Albuquerque, NM, United States of America

Antoine Farid Dagher